Register Description by Block
ADE3800
Register Name
ANA_LVDSANA5
ANA_LVDSANA7
Table 41: LVDS/RSDS Registers (Sheet 3 of 5)
Address Bits Mode Rst
Description
0065
0067
[7]
R/W C0
[6]
[5]
[4:0]
[7]
R
00
[6]
[5]
[4]
[3]
[2]
[1:0]
LVDS B power control
(for LVDS Channel [7:4], LVDS clk 1)
0: on
1*: off
LVDS A power control
(for LVDS Channel [3:0], LVDS clk 0)
0: on
1*: off
Output mode select
0*: RSDS (also powers down PLL)
1: LVDS
LVDS Iref Bias current setting
10000: 420uA
00011: 168uA
00010: 178uA
00001: 189uA
00000*: 201uA (normal)
11111: 202uA
11110: 216.3uA
11101: 233uA
11100: 252uA
LVDS Channel [7:4] power status
LVDS Channel [3:0] power status
LVDS/RSDS/PLL Global Power status
PLL powerdown status = [ANA_LVDSANA4[0] OR
ANA_LVDSANA2[7] OR (NOT ANA_LVDSANA5[5])]
PLL up status
PLL down status
PLL range status
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