ADE3800XT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ADE3800XT

Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters

STMicroelectronics 

ADE3800

Register Description by Block

4.20 Pulse Width Modulation (PWM)

The Pulse Width Modulation block generates two signals that can be used to control backlight

inverter switching power components directly. It is derived from XCLK and can be powered up

independently of the DOTCLK and INCLK domains. The frequency, duty cycle, polarity and overlap/

non-overlap are programmable. The output frequency can be free-running or locked to the output

vsync signal.

Table 43: PWM Registers (Sheet 1 of 2)

Register Name

PWM_CTRL0

PWM_CTRL1

PWM_PERIOD_L

PWM_PERIOD_U

PWM_DUTY_L

PWM_DUTY_U

PWM_OVERLAP_L

PWM_OVERLAP_U

Addr

01A0

01A1

01A2

01A3

01A4

01A5

01A6

01A7

Mode Bits Default

Description

R

[7] 00

R/W

[6]

R/W

[5]

R/W

[4]

R/W

[3]

R/W

[2]

R/W

[1]

R/W

[0]

R/W

[7:4] 00

R/W

[3:0]

R/W

[7:0] 00

R/W

[7:0] 00

R/W

[7:0] 00

R/W

[7:0] 00

R/W

[7:0] 00

R/W

[7:0] 00

PWM status

0*: unlocked

1: locked

0*: lock to CYCLES_PER_FRAME from the

free-running state machine

1: lock to CYCLES_PER_FRAME register

setting

PWM_A polarity

0*: active low

1: active high

PWM_B polarity

0*: active low

1: active high

0*: normal operation

1: force both PWM outputs to polarity settings

of bits 5 and 4

0*: change period or duty cycle at the end of

the current cycle

1: smooth change, period or duty cycle

increment/decrement every

PWM_STEP_DELAY cycle

0*: free-running

1: lock to out_vsync

0*: disable PWM output

1: enable PWM output

Lock 2nd order gain (power of 2)

0*: max

3: typical

F: min.

Lock gain (power of 2)

0*: max

6: typical

F: min.

Period-2 in free-running mode, in XCLKs

Duty cycle of PWM in XCLKs

Non-overlap of PWMs in XCLKs

119/138

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