ADE3800
Register Description by Block
Register Name
ANA_LVDSSW_VC
ANA_LVDSCOMPV
Table 41: LVDS/RSDS Registers (Sheet 4 of 5)
Address Bits Mode Rst
Description
0068
0069
[6:4] R/W 00
[3:0]
[6:4]
00
[2:0]
LVDS & RSDS Output Common Mode Adjustment
0*: 1.093V
1: 1.119V
2: 1.145V
3: 1.171V (normal)
4: 1.197V
5: 1.223V
6: 1.259V
7: 1.274V
LVDS & RSDS Swing Adjustment
0*: 170mV (normal)
F: 475mV
LSB = 20mV (typ)
VRL regulator current adjust
0*: off
1: 18uA (normal)
2: 36uA
3: 54uA
4: 72uA
5: 90uA
6: 108uA
7: 126uA
VRH regulator current adjust
0*: off
1: 18uA (normal)
2: 36uA
3: 54uA
4: 72uA
5: 90uA
6: 108uA
7: 126uA
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