ADE3800SXT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ADE3800SXT

Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters

STMicroelectronics 

ADE3800

Register Description by Block

OUTPUT INTERFACE

PIN #

(LQFP

128)

PIN #

(LQFP

100)

(RSDS

INPUT

NAME) PIN

NAME

LVDS

OUTPUT MODE

RSDS (LQFP-128)

RSDS (LQFP-100)

70

58

TCON0

71

59

TCON1

72

60

TCON2

73

61

TCON3

74

62

TCON4

75

63

TCON5

76

64

TCON6

77

65

TCON7

pwm_en ?

pwm_b: tcon0

pwm_en ?

pwm_a: tcon1

tcon2

tcon3

tcon4

tcon5

tcon6

tcon7

TCON

SIGNALS

pwm_en ?

pwm_b: tcon0

pwm_en ?

pwm_a: tcon1

tcon2

tcon3

tcon4

tcon5

tcon6

tcon7

TCON

SIGNALS

pwm_en ?

pwm_b: tcon0

pwm_en ?

pwm_a: tcon1

tcon2

tcon3

tcon4

tcon5

tcon6

tcon7

TCON

SIGNALS

Debug Mode

If LVDS debug mode is enabled (omux_test[0] = 1), LVDS output data will be set to a static 7-bit

pattern which is programmed in omux_ctrl4[6:0]

If RSDS debug mode is enabled (omux_test[1] = 1), RSDS output data will be set to a static pattern

which is programmed in omux_ctrl4[1:0].

4.17.2 Output Clocks

Output clock (to LVDS PLL) for both functional and test modes is the divide-by-2 clock generated

inside omux. This clock is flopped on the falling edge of fsyn_outclk providing a ¼ phase offset

between clock and data.

RSDS output clocks 0 & 1 are set to fsyn_outclk_div2_dly for both functional and test modes. This

clock has a programmable delay offset from the fsyn_outclk_div2. This is to ensure that data will

meet the setup/hold requirements at the destination (panel.)

The out_enab signal (from the TCON block) must be programmed so that its left (rising) edge is odd

in 2 ppc RSDS mode.

4.17.3 Clock Sources and Timing Considerations

The omux block operates on dotclk with the exception of omux_mux which runs on fsyn_outclk.

Table 2.4 describes the relationship between fsyn_outclk, fsyn_outclk_div2 and dotclk.

Table 36: Clock relationship

1 ppc

2 ppc

fsyn_outclk_freq

dotclk source sel

GLBL_CLK_SRC_SEL_0[6:4]

GLBL_CLK_SRC_SEL_1[6:4]

2x dotclk_freq

dotclk_freq

fsyn_outclk_div2 half

speed

2

fsyn_outclk full speed

3

3

3

FSYN_PR_OTCLK

2^22 * xclk_freq /

dotclk_freq

2^21 * xclk_freq /

dotclk_freq

101/138

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