ADE3800
Register Description by Block
Register Name
TCON_PULSE_4_SET_L
TCON_PULSE_4_SET_U
TCON_PULSE_4_RST_L
TCON_PULSE_4_RST_U
TCON_PULSE_5_SET_L
TCON_PULSE_5_SET_U
TCON_PULSE_5_RST_L
TCON_PULSE_5_RST_U
Table 39: Register Map (Sheet 4 of 7)
Addr. Bits Mode Rst
0B28
0B29
0B2A
0B2B
0B2C
0B2D
0B2E
0B2F
refer to TCON_PULSE_0
refer to TCON_PULSE_0
Description
TCON_WINDOW_0_LEFT_L
TCON_WINDOW_0_LEFT_U
TCON_WINDOW_0_RIGHT_L
TCON_WINDOW_0_RIGHT_U
TCON_WINDOW_0_TOP_L
TCON_WINDOW_0_TOP_U
TCON_WINDOW_0_BOTTOM_L
TCON_WINDOW_0_BOTTOM_U
0B30
0B31
0B32
0B33
0B34
0B35
0B36
0B37
TCON_WINDOW_1_LEFT_L
TCON_WINDOW_1_LEFT_U
TCON_WINDOW_1_RIGHT_L
TCON_WINDOW_1_RIGHT_U
TCON_WINDOW_1_TOP_L
TCON_WINDOW_1_TOP_U
TCON_WINDOW_1_BOTTOM_L
TCON_WINDOW_1_BOTTOM_U
TCON_WINDOW_2_LEFT_L
TCON_WINDOW_2_LEFT_U
TCON_WINDOW_2_RIGHT_L
TCON_WINDOW_2_RIGHT_U
TCON_WINDOW_2_TOP_L
TCON_WINDOW_2_TOP_U
TCON_WINDOW_2_BOTTOM_L
TCON_WINDOW_2_BOTTOM_U
0B38
0B39
0B3A
0B3B
0B3C
0B3D
0B3E
0B3F
0B40
0B41
0B42
0B43
0B44
0B45
0B46
0B47
[7:0]
R/W
00
[3:0]
R/W
00
[7:0]
R/W
00
[3:0]
R/W
00
[7:0]
R/W
00
[3:0]
R/W
00
[7:0]
R/W
00
[4]
R/W
00
[3:0]
R/W
refer to TCON_WINDOW_0
left edge compare count
left edge compare count
right edge compare count
right edge compare count
top edge compare count
top edge compare count
bottom edge compare count
0*: window
1: pulse start at (left, top), end at (right, bottom)
bottom edge compare count
refer to TCON_WINDOW_0
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