ADE3800
Register Description by Block
Table 37: Polarity programming examples.
polarity type
vmask pulse length
pol toggle every line, invert frame to frame, steady during vblank (2
frame sequence)
polarity toggle every other line, invert frame to frame, steady during
vblank (2 frame sequence)
polarity toggle every 3rd line, invert frame to frame, steady during
vblank (2 frame sequence)
polarity toggle every other line, walking pattern (4 frame sequence)
odd, usually vpixel+1 or vpixel-1
odd*2, usually vpixel+2 or vpixel -2
odd*3
odd, usually vpixel+1 or vpixel-1
vlen
0
1
2
1
Table 38: Video Pipeline Latency information
Block
PGEN (*)
SRGB (*)
GAMMA
OSD (*)
APC
TCON
LVDS (pixel delay up to LVDS Tx)
RSDS (delay up to the RSDS pads)
Output pixel video pipeline latency
(in per block dotclk units)
+3 (+16 vs TCON window H values)
+6 (+13 vs TCON window H values)
+3
+3 (+4 vs TCON window H values)
+1
Zero Reference
1ppc: 5 pixels, 2ppc 6 pixels
1ppc: 5 pixels,
2ppc w/ split line buffer=640:
640+12 pixels
(*): Block having a window control feature
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