Register Description by Block
ADE3800
Register Name
TCON_CTRL
TCON_POLARITY_CTRL
TCON_INV_0
Table 39: Register Map (Sheet 1 of 7)
Addr. Bits Mode Rst
Description
0B00 [6:4]
[3:2]
[0]
0B01 [7:6]
[5:4]
[2:0]
0B02 [7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
R/W
00
out_venab source selection
0*: out_venab generated from
out_enab (normal)
1: tcon_pgen
2: window venab[0]
3: window venab[1]
4: window venab[2]
5: window venab[3]
6-7: reserved
R/W
i2c block transfer (not tcon) event selection
0*: (hcount == 0) && (vcount == 0)
1: (hcount == 0)
2: srtd0
3: srtd1
R/W
TCON[7:0] output enable. Internal signals
are always active.
R/W
00
vlen = toggle/polarity line sequence length
(desired – 1)
R/W
vtoggle / polarity horizontal reference (1 of
4 comparators)
R/W
polarity vmask selection
0*: pulse 0
1: pulse 1
2: pulse 2
3: pulse 3
4: pulse 4
5: pulse 5
6: pulse 0, reset vtog_count to 0 at rising
edge of vmask, polarity reset to 0
7: pulse 0, resync vtog_count to 1 at ris-
ing edge of vmask, polarity reset to 0
Note: pulse type must be vertical
R/W
00
invert output tcon7
R/W
invert output tcon6
R/W
invert output tcon5
R/W
invert output tcon4
R/W
invert output tcon3
R/W
invert output tcon2
R/W
invert output tcon1
R/W
invert output tcon0
106/138