ADE3800SXT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ADE3800SXT

Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters

STMicroelectronics 

Register Description by Block

ADE3800

Register Name

SRT_CSYNC_INV

SRT_CSYNC_THR_L

SRT_CSYNC_THR_U

SRT_VSYNC_SEL

SRT_VSYNC_THR_L

SRT_VSYNC_THR_U

SRT_COAST_VS_SEL

SRT_COAST_RISE_L

SRT_COAST_RISE_M

SRT_COAST_RISE_U

SRT_COAST_FALL_L

SRT_COAST_FALL_M

SRT_COAST_FALL_U

SRT_HS_CTRL

Table 16: Sync Retiming Registers (Sheet 1 of 2)

Addr Mode Bits Rst

Description

01E0 R/W

R/W

R/W

R/W

01E1 R/W

01E2 R/W

01E3 R/W

01E4 R/W

01E5 R/W

01E6 R/W

R/W

01E7 R/W

01E8 R/W

01E9 R/W

01EA R/W

01EB R/W

01EC R/W

01EE R/W

R/W

[2]

00 invert vert sync signal extracted from internal SOG

comparator (sog_vs_inv)

[1]

invert vert sync extracted from composite sync signal on

HSync pin (csync_vs_inv)

[0]

invert filtered vert sync (filt_vs_inv)

[7:0] 80 composite sync vertical sync extractor threshold

(this is the narrowest HSync signal sent +50% as a

safety margin) refer to Figure 7

[3:0] 00

[2:0] 00 filtered vert sync source select

0*: VSYNC pin

1: vsync from composite HSYNC pin

2: vsync from composite SOG[0] comparator

3: vsync from composite SOG[1] comparator

4: vsync from composite SOG[2] comparator

5: vsync from alternate SOG source

6 - 7: Reserved

[7:0] 80 filtered vert sync delay

[3:0] 00

[3]

00 coast signal trigger edge

0*: rising edge of selected VSync

1: falling edge of selected VSync

[2:0]

source selection for coast VSync trigger

0*: VSYNC pin

1: vsync from composite HSYNC pin

2: vsync from composite SOG[0] comparator

3: vsync from composite SOG[1] comparator

4: vsync from composite SOG[2] comparator

5: filtered and delayed vsync (normal)

6: vsync from alternate SOG source

7: Reserved

[7:0] 00 rising edge of coast, in XCLKs from vsync trigger

[7:0] 00

[7:0] 00

[7:0] 00 falling edge of coast, in XCLKs from vsync trigger

[7:0] 00

[7:0] 00

[4]

00 Edge of inclk on which to sample horizontal sync:

0*: rising edge

1: falling edge (normal)

[2:0]

HSync Sample Selection for SMUX

0*: reserved

1: llk_HSync (normal)

2: SOG0

3: SOG1

4: SOG2

5: EXT_SOG

34/138

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