ADE3800SXL View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ADE3800SXL

Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters

STMicroelectronics 

Register Description by Block

ADE3800

Register Name

SMEAS_STATUS_MASK2

SMEAS_ACT_POLLING

SMEAS_ANA_ACT

SMEAS_SOG_DLY12

SMEAS_SOG_DLY34

SMEAS_ANA_STUCK

SMEAS_XK_PER_H_L

SMEAS_XK_PER_H_M

SMEAS_XK_PER_H_U

SMEAS_XK_PER_V_L

SMEAS_XK_PER_V_M

SMEAS_XK_PER_V_U

SMEAS_H_PER_V_L

SMEAS_H_PER_V_U

SMEAS_XK_V_HI_L

SMEAS_XK_V_HI_M

SMEAS_XK_V_HI_U

SMEAS_REF_FASTMU_L

SMEAS_REF_FASTMU_U

SMEAS_STATUS_TMOT

Table 17: SMEAS Register Definitions (Sheet 5 of 6)

Addr Mode Bits Rst

Description

0135 R/W

R/W

013F R

0140 R

R

R

R

R

R

R

R

0141 R

R

0142 R

R

0143 R

R

R

R

R

0146 R

0147 R

0148 R

0149 R

014A R

014B R

014C R

014D R

014E R

014F R

0150 R

0132 R/W

0133 R/W

0151 R

R

[1]

00 Enable mute function to respond to

SMEAS_STATUS_RANGE2[1].

[0]

Enable mute function to respond to

SMEAS_STATUS_RANGE2[0].

[0]

00 Activity detection polling bit.

Toggles when new results are ready in free-run. Undefined in

one-shot mode.

[7]

00 SOG2 is active

[6]

SOG1 is active

[5]

SOG0 is active

[4]

EXT_SOG pin is active

[3]

Comp vsync from EXT_SOG pin is active

[2]

Comp vsync from HSYNC pin is active

[1]

HSYNC pin is active

[0]

VSYNC pin is active

[7:4] 00 d2: delay in xclks between SOG1 & SOG2 falling edges

[3:0]

d1: delay in xclks between SOG0 & SOG1 falling edges

[7:4] 00 d4: delay in xclks between SOG1 & SOG0 rising edges

[3:0]

d3: delay in xclks between SOG2 & SOG1 rising edges

[4]

00 EXT_SOG is stuck at 1(high)/0(low)

[3]

Comp vsync from EXT_SOG is stuck at 1(high)/0(low)

[2]

Comp vsync from HSYNC pin is stuck at 1(high)/0(low)

[1]

HSYNC pin is stuck at 1(high)/0(low)

[0]

VSYNC pin is stuck at 1(high)/0(low)

[7:0] 00 Xclks per Horizontal [7:0] (result = actual - 2)

[7:0] 00 Xclks per Horizontal [15:8]

[7:0] 00 Xclks per Horizontal [23:16]

[7:0] 00 Xclks per Vertical [7:0]

[7:0] 00 Xclks per Vertical [15:8]

[7:0] 00 Xclks per Vertical [23:16]

[7:0] 00 Horizontal per Vertical [7:0]

[7:0] 00 Horizontal per Vertical [15:8]

[7:0] 00 Xclks per V high

[7:0] 00

[7:0] 00

[7:0] 00 Fastmute reference, xclks per hsync, one line only

[3:0] 00

[1]

00 Indicates that the horizontal measurement timed out. Can

only be cleared by sync reset or smeas all_clear.

[0]

Indicates that the vertical measurement timed out. Can only

be cleared by sync reset or smeas all_clear.

42/138

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