ADE3800SXL View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ADE3800SXL

Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters

STMicroelectronics 

ADE3800

Register Description by Block

Note:

The digital loop filter is controlled by two parameters: A and B. The A and B parameters control the

response of the 2nd order digital filter. A and B are exponential coefficients. The relationship of

these numbers to the classic 2nd order damping and natural frequency are as follows:

● Damping = 2^(AE-8) * SQRT(5 * MFACTOR / (2^(BE+4)))

● Natural Frequency = SQRT(MFACTOR * 5 * 2^(BE-30))

Typical value for the A and B parameters is 66h.

The synthesized HSync supplied to SMUX is 50% duty cycle.

Table 15: Line Lock PLL Registers (Sheet 1 of 2)

Register Name

LLK_CTRL

LLK_SYNC_OFFSET_MODE

LLK_MFACTOR_L

LLK_MFACTOR_U

LLK_PHASE_RATE_INIT

LLK_TC_AEF

LLK_TC_BEF

LLK_TC_AES

LLK_TC_BES

LLK_LOCK_TOL

LLK_LOCK_LINE_NB

Addr Mode Bits

0800 R/W [6]

R/W [5]

R/W [4]

R/W [3:1]

R/W [0]

0801 R/W [3]

R/W [2]

R/W [1]

R/W [0]

0802 R/W [7:0]

0803 R/W [3:0]

0804 R/W [7:0]

0805 R/W [3:0]

0806 R/W [3:0]

0807 R/W [3:0]

0808 R/W [3:0]

0809 R/W [7:0]

080A R/W [7:0]

Rst

Description

00 0*: use slow filter when coarse error is zero

1: use slow filter when lock condition is achieved

mfactor shadow control

0*: simple shadow. Apply new mfactor when mfactor_u

is written.

1: shadow transfer on in_venab falling edge.

0*: lock to rising edge of input HSync

1: lock to falling edge of input HSync

input HSync select

0*: HSYNC pin

1: SOG0

2: SOG1

3: SOG2

4: EXT_SOG

LLK pll free run enable

06 manual resync mode

The LLK pll requires a resync after any change of

mfactor or offset. Writing to this bit causes a one-time

resync of the PLL accumulator (cleared by H/W).

resync every frame modea

resync on in_venab falling edge1

resync on in_venab rising edge1

80 mfactor[7:0] = in_htotal

02 mfactor[11:8]

80 pll phase rate init

freq = xclk_freq * 128 / phase_rate_init.

0A time constant A when out of lock

0A time constant B when out of lock

06 time constant A when in lock

06 time constant B when in lock

20 error limit for determining lock. LSB = 150ps (typ)

30 line count for determining lock.

- set when error is < lock_tol for lock_line_nb of lines.

- cleared if error exceeds lock_tol.

31/138

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