ADE3800SXL View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADE3800SXL
STMicroelectronics
ADE3800SXL Datasheet PDF : 138 Pages
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Register Description by Block
ADE3800
Table 15: Line Lock PLL Registers (Sheet 2 of 2)
Register Name
Addr Mode Bits Rst
Description
LLK_OFFSET_L
LLK_OFFSET_U
080B R/W [7:0]
080C R/W [1:0]
00 phase offset [7:0] of adc sample clock. LSB is
xclk_period/512 = 72ps.
00 phase offset
LLK_PULSE_HIGH_EXT
080D R/W [7]
00 inclk pulse extend enable
R/W [2:0]
inclk pulse extend value. LSB = 0.3ns (typ)
LLK_PHASE_RATE_MIN
080E R/W [7:0]
14 phase rate minimum. Sets the upper frequency limit of
the PLL.
phase_rate_min = xclk_freq * 128 / max_inclk_freq.
LLK_STAT_LINE_NB_L
LLK_STAT_LINE_NB_U
080F R/W [7:0]
0810 R/W [7:0]
40 number of lines over which statistics are gathered
00 number of lines over which statistics are gathered
LLK_STAT_SUM_ABS_MAX_L 0811 R/W [7:0]
LLK_STAT_SUM_ABS_MAX_U 0812 R/W [7:0]
60 limit for sum of absolute errors
00
LLK_STAT_MAX_ABS_MAX
0813 R/W [7:0]
04 limit for absolute error
LLK_DEADZONE
0814 R/W [3:0]
02 coarse error deadzone, normal operation = 2.
LLK_STATUS
0830 R
[4]
00 max absolute error exceeded limit, not sticky
R
[3]
sum of absolute errors exceeded limit, not sticky
R
[2]
pll filter overflow condition, not sticky
R
[1]
coarse error is zero status, not sticky
R
[0]
lock status, not sticky
LLK_STATUS_PHASE_RATE_I_ 0831 R
[7:0]
0
LLK_STATUS_PHASE_RATE_I_ 0832 R/W [7:0]
1
LLK_STATUS_PHASE_RATE_I_ 0833 R/W [7:0]
2
LLK_STATUS_PHASE_RATE_I_ 0834 R/W [5:0]
3
00 pll phase rate, free running readout.b
00
00
00
LLK_STATUS_SUM_ABS_L
LLK_STATUS_SUM_ABS_U
0835 R
0836 R
[7:0]
00 sum of absolute errors readout
[7:0]
00
LLK_STATUS_MAX_ABS
0837 R
[7:0]
00 max absolute error readout
LLK_MFACTOR_HW_L
LLK_MFACTOR_HW_U
0842 R
0843 R
[7:0]
80 mfactor shadow hw readout
[7:0]
02
LLK_TEST
084F R/W [7:0]
00 reserved
a. recommended setting for bits [2:0] = 110b
b. phase rate period (in picoseconds) is:
haseRate(ps)= -L---l--k---S-----t--a---t--u----s---P-----h---a----s---e----R-----a----t--e---[---2---8----…----0---]----×------2---–---2--1-----×-----X-----T----A----L----p---e----r---i-o----d----(--p----s--
128
Example:
LLK_STATUS_PHASE_RATE_I_[28:0] = 03335BDF , XTAL = 27 MHz
phase rate period = 7.409 ns
frequency = 134.97 MHz
32/138
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