ADE7816ACPZ-RL View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADE7816ACPZ-RL

Six Current Channels, One Voltage Channel Energy Metering IC

Analog Devices 

ADE7816

Data Sheet

The reactive energy register content overflows from full-scale

positive (0x7FFFFFFF) to full-scale negative (0x80000000) and

continues to increase in value when the reactive power is positive.

Setting Bit 6 (RSTREAD) of the LCYCMODE (Address 0xE702)

register enables a read-with-reset for all reactive energy accu-

mulation registers. When this bit is set, all energy accumulation

registers are set to 0 following a read operation.

LINE CYCLE ACCUMULATION MODE

In the active and reactive line cycle accumulation mode, the

energy accumulation of the ADE7816 is synchronized to the

voltage channel zero crossing, so that the active and reactive

energy can be accumulated over an integral number of half line

cycles. This feature is available for the active and reactive energy

accumulation on all six channels. The advantage of summing

the active and reactive energy over an integral number of half

line cycles is that the sinusoidal component of the energy is

reduced to 0. This eliminates any ripple in the energy calculation.

Accurate energy is calculated in a shorter time because the

integration period can be shortened. The line cycle accumulation

mode can be used for fast calibration and to obtain the average

power over a specified time period. Figure 30 shows a diagram

of the active energy line cycle accumulation mode signal path.

Active and reactive energy line cycle accumulation modes are

disabled by default and can be enabled on all six channels by setting

Bit 0 (LWATT) and Bit 1 (LVAR), respectively, in the LCYCMODE

register. Bit 3 (ZX_SEL) of the LCYCMODE register must also be

set to enable the voltage channel zero-crossing counter to be used

in the line cycle accumulation measurement. The accumulation

time should be written to the LINECYC register (Address 0xE60C)

as an integer number of half line cycles. The ADE7816 can

accumulate energy for up to 65,535 half line cycles. This equates

to an accumulation period of approximately 655 sec with 50 Hz

inputs, and 546 sec with 60 Hz inputs.

The number of half line cycles written to the LINECYC register

is used for the active and reactive line cycle accumulation on all

six channels. At the end of a line cycle accumulation period, the

xWATTHR and xVARHR registers are updated and the LENERGY

flag is set in the STATUS0 register (Address 0xE502). If the

LENERGY bit in the MASK0 register (Address 0xE50A) is set,

an external interrupt is issued on the IRQ0 pin. Another accu-

mulation cycle begins immediately, as long as the LWATT and

LVAR bits in the LCYCMODE register remain set.

The contents of the xWATTHR and xVARHR registers are updated

synchronous to the LENERGY flag. The xWATTHR and xVARHR

registers hold their current values until the end of the next line

cycle period, when the contents are replaced with the new reading

(see Figure 30 and Figure 31). When using the line cycle accu-

mulation mode, Bit 6 (RSTREAD) of the LCYCMODE register

should be set to Logic 0 because the read-with-reset function of

the energy registers is not available in this mode.

Note that, when line cycle accumulation mode is first enabled,

the reading after the first LENERGY flag should be ignored

because it may be inaccurate. This inaccuracy is due to the line

cycle accumulation mode not being synchronized to the zero

crossing. As a result, the first reading may not be taken over

a complete number of half line cycles. After the first line cycle

accumulation is completed, all successive readings are correct.

OUTPUT

FROM

LPF

xWATTOS

++

xWGAIN

48

0

INTERNAL

ACCUMULATION

WTHR[48:0]

OUTPUT FROM

VOLTAGE CHANNEL

ADC

LPF_ZX

ZERO-CROSSING

DETECTION

CALIBRATION

CONTROL

15 LINECYC 0

Figure 30. Line Cycle Accumulation for xWATTHR

23 xWATTHR 0

OUTPUT FROM

REACTIVE POWER

ALGORITHM

OUTPUT FROM

VOLTAGE CHANNEL

ADC

xVAROS

++

xVARGAIN

48

0

INTERNAL

ACCUMULATION

VARTHR[48:0]

LPF_ZX

ZERO-CROSSING

DETECTION

CALIBRATION

CONTROL

15 LINECYC 0

Figure 31. Line Cycle Accumulation for xVARHR

Rev. 0 | Page 22 of 48

23 xVARHR 0

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