ADE7816ACPZ-RL View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADE7816ACPZ-RL Datasheet PDF : 48 Pages
| |||
ADE7816
CHECKSUM
The ADE7816 has a 32-bit checksum register (Address 0xE51F)
that ensures that certain important configuration registers maintain
their desired value during normal operation.
The registers that are included in this feature are MASK0,
MASK1, COMPMODE, gain, CONFIG, MMODE, ACCMODE,
LCYCMODE, HSDC_CFG, plus four additional 16-bit reserved
registers and six 8-bit reserved internal registers. All reserved
registers always have default values. The ADE7816 computes the
cyclic redundancy check (CRC) based on the IEEE802.3 standard.
The registers are introduced, one by one, into a linear feedback
shift register (LFSR) based generator, starting with the least
significant bit (as shown in Figure 36). The 32-bit result is written
in the checksum register. After power-up or a hardware/software
reset, the CRC is computed on the default values of the registers.
The default value of the checksum register is 0x33666787.
Figure 37 shows how the LFSR works. The MASK0, MASK1,
COMPMODE, gain, CONFIG, MMODE, ACCMODE,
LCYCMODE, and HSDC_CFG registers, along with the four
16-bit reserved registers and six 8-bit reserved internal registers,
form the Bits[a255, a254, …, a0] used by the LFSR. Bit a0 is the least
significant bit of the first internal register to enter the LFSR;
Bit a255 is the most significant bit of the MASK0 register, the last
register to enter the LFSR. The formulas that govern the LFSR
are as follows:
bi(0) = 1, where i = 0, 1, 2, …, 31, the initial state of the bits that
form the CRC. Bit b0 is the least significant bit, and Bit b31 is the
most significant bit.
Data Sheet
gi, where i = 0, 1, 2, …, 31 is the coefficient of the generating
polynomial defined by the IEEE802.3 standard as follows:
G(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 +
(18)
x8 + x7 + x5 + x4 + x2 + x + 1
g0 = g1 = g2 = g4 = g5 = g7 = 1
(19)
g8 = g10 = g11 = g12 = g16 = g22 = g26 = g31 = 1
All of the other gi coefficients are equal to 0.
FB(j) = aj − 1 XOR b31(j − 1)
(20)
b0(j) = FB(j) AND g0
(21)
bi(j) = FB(j) AND gi XOR bi − 1(j − 1), i = 1, 2, 3, ..., 31 (22)
Equation 20, Equation 21, and Equation 22 must be repeated for
j = 1, 2, …, 256. The value written into the checksum register con-
tains Bit bi(256), i = 0, 1, …, 31. After the bits from the reserved
internal register pass through the LFSR, the value of the CRC
(which is obtained at Step j = 48) is 0x33660787.
Two different approaches can be followed in using the checksum
register. One is to compute the CRC, based on Equation 18 to
Equation 22, and then compare the value against the checksum
register. Another is to periodically read the checksum register.
If two consecutive readings differ, it can be assumed that one of
the registers has changed value and that, therefore, the ADE7816
configuration has changed. The recommended response is to
initiate a hardware/software reset that sets the values of all
registers (including the reserved ones) to the default, and then
reinitialize the configuration registers.
31 0 31 0 15
0 15 0 15
0
MASK0 MASK1 COMPMODE GAIN RESERVED
255 248 240
232 224
216
7
07
07
0
INTERNAL INTERNAL INTERNAL
REGISTER REGISTER REGISTER
7
0
INTERNAL
REGISTER
7
0
INTERNAL
REGISTER
7
0
INTERNAL
REGISTER
40
32
24
16
87
0
Figure 36. Checksum Register Calculation
LFSR
GENERATOR
g0
g1
g2
g3
b0
b1
b2
LFSR
g31
FB
b31
a255, a254,....,a2, a1, a0
Figure 37. LFSR Generator Used in Checksum Register Calculation
Rev. 0 | Page 30 of 48
Share Link: 