ADE7816ACPZ-RL View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADE7816ACPZ-RL Datasheet PDF : 48 Pages
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Data Sheet
HSDC Interface Timing
Table 4. HSDC Interface Timing Parameter
Parameter
HSA to HSCLK Edge
HSCLK Period
HSCLK Low Pulse Width
HSCLK High Pulse Width
Data Output Valid After HSCLK Edge
Data Output Fall Time
Data Output Rise Time
HSCLK Rise Time
HSCLK Fall Time
HSD Disable After HSA Rising Edge
HSA High After HSCLK Edge
Symbol
tSS
tSL
tSH
tDAV
tDF
tDR
tSR
tSF
tDIS
tSFS
Min
0
125
50
50
5
0
HSA
tSS
tSFS
HSCLK
tDAV
HSD
tSL
tSH
tSF
tSR
tDIS
MSB
INTERMEDIATE BITS
tDF
Figure 4. HSDC Interface Timing
LSB
tDR
Load Circuit for All Timing Specifications
2mA
IOL
TO OUTPUT
PIN CL
50pF
800µA
IOH
1.6V
Figure 5. Load Circuit for All Timing Specifications
ADE7816
Max
Unit
ns
ns
ns
ns
40
ns
20
ns
20
ns
10
ns
10
ns
ns
ns
Rev. 0 | Page 7 of 48
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