ADE7880ACPZ-RL(RevA) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADE7880ACPZ-RL
(Rev.:RevA)

Polyphase Multifunction Energy Metering IC with Harmonic Monitoring

Analog Devices 

ADE7880

Data Sheet

to 750 ms, the settling time of the harmonic calculations. Other

possible values are 500 ms (HSTIME = 00), 1 sec (10) and 1250

ms (11).

The second approach, enabled when Bit 0 (HRCFG) of

HCONFIG register is set to 1, sets Bit 19 (HREADY) in

STATUS0 register to 1 every time the harmonic calculations are

updated at the update frequency determined by HRATE bits

without waiting for the harmonic calculations to settle. This

allows an external microcontroller to access the harmonic

calculations immediately after they have been started. If the

corresponding mask bit in the MASK0 interrupt mask register

is enabled, the IRQ pin also goes active low. The status bit is

• Initialize the gain registers used in the harmonic

calculations. Leave the offset registers to 0.

• Read the registers in which the harmonic information is

stored using the burst or regular reading mode at high to

low transitions of CF2/HREADY pin.

WAVEFORM SAMPLING MODE

The waveform samples of the current and voltage waveform,

the active, reactive, and apparent power outputs are stored

every 125 μs (8 kHz rate) into 24-bit signed registers that can be

accessed through various serial ports of the ADE7880. Table 22

provides a list of registers and their descriptions.

cleared and the pin IRQ is set to high again by writing to the

STATUS0 register with the corresponding bit set to 1.

Additionally, the ADE7880 provides a periodical output signal

called HREADY at the CF2/HREADY pin synchronous to the

moment the harmonic calculations are updated in the harmonic

registers. This functionality is chosen if Bit 2 (CF2DIS) is set to

1 in the CONFIG register. If CF2DIS is set to 0 (default value),

the CF2 energy to frequency converter output is provided at

CF2/HREADY pin. The default state of this signal is high. Every

time the harmonic registers are updated based on HRATE bits

in HCONFIG register, the signal HREADY goes low for

approximately 10 μsec and then goes back high. If Bit 0

(HRCFG) in the HCONFIG register is 0, that is the HREADY

bit in the STATUS1 register is set to 1 every HRATE period

right after the harmonic calculations have started, the signal

HREADY toggles high, low and back synchronously. If the

HRCFG bit is 1, that is, Bit HREADY in the STATUS1 register

is set to 1 after the HSTIME period, the HREADY signal toggles

high, low and back synchronously. The HREADY signal allows

fast access to the harmonic registers without having to use

HREADY interrupt in MASK1 register.

In order to facilitate the fast reading of the registers in which

the harmonic calculations are stored, a special burst registers

reading has been implemented in the serial interfaces. See the

I2C Read Operation of Harmonic Calculations Registers and the

SPI Read Operation sections for details.

Recommended Approach to Managing Harmonic

Calculations

The recommended approach to managing the ADE7880

harmonic calculations is the following:

• Set up Bit 2 (CF2DIS) in the CONFIG register. Set the

CF2DIS bit to 1 to use the CF2/HREADY pin to signal

when the harmonic calculations have settled and are

updated. The high to low transition of HREADY signal

indicates when to read the harmonic registers. Use the

burst reading mode to read the harmonic registers as it is

the most efficient way to read them.

• Choose the harmonics to be monitored by setting HX, HY

and HZ appropriately.

• Select all the HCONFIG register bits.

Table 22. Waveform Registers List

Register

Description

IAWV

Phase A current

VAWV

Phase A voltage

IBWV

Phase B current

VBWV

Phase B voltage

ICWV

Phase C current

VCWV

Phase C voltage

INWV

Neutral current

AVA

Phase A apparent power

BVA

Phase B apparent power

CVA

Phase C apparent power

AWATT

Phase A active power

BWATT

Phase B active power

CWATT

Phase C active power

Bit 17 (DREADY) in the STATUS0 register can be used to

signal when the registers listed in Table 22 can be read using

I2C or SPI serial ports. An interrupt attached to the flag can be

enabled by setting Bit 17 (DREADY) in the MASK0 register. (see

the Digital Signal Processor section for more details on

Bit DREADY).

The ADE7880 contains a high speed data capture (HSDC) port

that is specially designed to provide fast access to the waveform

sample registers. Read the HSDC Interface section for more

details.

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.

All registers listed in Table 22 are transmitted signed extended

from 24 bits to 32 bits (see Figure 44).

ENERGY-TO-FREQUENCY CONVERSION

The ADE7880 provides three frequency output pins: CF1, CF2,

and CF3. The CF2 pin is multiplexed with the HREADY pin of

the harmonic calculations block. When HREADY is enabled,

the CF2 functionality is disabled at the pin. The CF3 pin is

multiplexed with the HSCLK pin of the HSDC interface. When

HSDC is enabled, the CF3 functionality is disabled at the pin.

CF1 pin is always available. After initial calibration at manu-

facturing, the manufacturer or end customer verifies the energy

meter calibration. One convenient way to verify the meter

calibration is to provide an output frequency proportional to the

Rev. A | Page 64 of 104

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