ADE7880ACPZ-RL(RevA) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADE7880ACPZ-RL
(Rev.:RevA)
(Rev.:RevA)
Analog Devices
ADE7880ACPZ-RL Datasheet PDF : 104 Pages
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ADE7880
Data Sheet
By default, the TERMSELx bits are all 1 and the CF1SEL bits are
000, the CF2SEL bits are 100, and the CF3SEL bits are 010. This
means that by default, the CF1 digital-to-frequency converter
produces signals proportional to the sum of all 3-phase total
active powers, CF2 produces signals proportional to fundamental
reactive powers, and CF3 produces signals proportional to
apparent powers.
Similar to the energy accumulation process, the energy-to-
frequency conversion is accomplished in two stages. The first
stage is the same stage illustrated in the energy accumulation
sections of active, reactive and apparent powers (see Active
Energy Calculation, Fundamental Reactive Energy Calculation,
Apparent Energy Calculation sections). The second stage
consists of the frequency divider by the CFxDEN 16-bit
unsigned registers. The values of CFxDEN depend on the meter
constant (MC), measured in impulses/kWh and how much
energy is assigned to one LSB of various energy registers:
xWATTHR, xFVARHR, and so forth. Suppose a derivative of
Wh [10n Wh] where n is a positive or negative integer, is desired
as one LSB of xWATTHR register. Then, CFxDEN is as follows:
CFxDEN
=
103
MC[imp/kwh] × 10n
(49)
The derivative of wh must be chosen in such a way to obtain a
CFxDEN register content greater than 1. If CFxDEN = 1, then
the CFx pin stays active low for only 1 μs. Thus, CFxDEN
register should not be set to 1. The frequency converter cannot
accommodate fractional results; the result of the division must be
rounded to the nearest integer. If CFxDEN is set equal to 0, then
the ADE7880 considers it to be equal to 1.
The CFx pulse output stays low for 80 ms if the pulse period is
larger than 160 ms (6.25 Hz). If the pulse period is smaller than
160 ms and CFxDEN is an even number, the duty cycle of the
pulse output is exactly 50%. If the pulse period is smaller than
160 ms and CFxDEN is an odd number, the duty cycle of the
pulse output is
(1+1/CFxDEN) × 50%
TERMSELx BITS IN
COMPMODE
INSTANTANEOUS
PHASE A
ACTIVE POWER
INSTANTANEOUS
PHASE B
ACTIVE POWER
INSTANTANEOUS
PHASE C
ACTIVE POWER
DIGITAL SIGNAL
PROCESSOR
CFxSEL BITS IN
CFMODE
VA
27
WATT
FWATT
INTERNAL
ACCUMULATOR
FVAR
THRESHOLD
34
27 26
0
27
WTHR
0
REVPSUMx BIT OF
STATUS0[31:0]
FREQ DIVIDER
CFxDEN
CFx PULSE
OUTPUT
Figure 87. Energy-to-Frequency Conversion
Rev. A | Page 66 of 104
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