ADE7880ACPZ-RL(RevA) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADE7880ACPZ-RL
(Rev.:RevA)

Polyphase Multifunction Energy Metering IC with Harmonic Monitoring

Analog Devices 

ADE7880

INTERRUPTS

The ADE7880 has two interrupt pins, IRQ0 and IRQ1. Each of the

pins is managed by a 32-bit interrupt mask register, MASK0 and

MASK1, respectively. To enable an interrupt, a bit in the MASKx

register must be set to 1. To disable it, the bit must be cleared

to 0. Two 32-bit status registers, STATUS0 and STATUS1, are

associated with the interrupts. When an interrupt event occurs

in the ADE7880, the corresponding flag in the interrupt status

register is set to a logic 1 (see Table 36 and Table 37). If the mask

bit for this interrupt in the interrupt mask register is logic 1,

then the IRQx logic output goes active low. The flag bits in the

interrupt status register are set irrespective of the state of the mask

bits. To determine the source of the interrupt, the MCU should

perform a read of the corresponding STATUSx register and

identify which bit is set to 1. To erase the flag in the status register,

write back to the STATUSx register with the flag set to 1. After an

interrupt pin goes low, the status register is read and the source of

the interrupt is identified. Then, the status register is written back

without any change to clear the status flag to 0. The IRQx pin

remains low until the status flag is cancelled.

By default, all interrupts are disabled. However, the RSTDONE

interrupt is an exception. This interrupt can never be masked

(disabled) and, therefore, Bit 15 (RSTDONE) in the MASK1

register does not have any functionality. The IRQ1 pin always

goes low, and Bit 15 (RSTDONE) in the STATUS1 register is set

to 1 whenever a power-up or a hardware/software reset process

ends. To cancel the status flag, the STATUS1 register has to be

written with Bit 15 (RSTDONE) set to 1.

Certain interrupts are used in conjunction with other status

registers. The following bits in the MASK1 register work in

conjunction with the status bits in the PHNOLOAD register:

• Bit 0 (NLOAD)

• Bit 1 (FNLOAD)

• Bit 2 (VANLOAD)

The following bits in the MASK1 register work with the status bits

in the PHSTATUS register:

• Bit 16, (SAG)

• Bit 17 (OI)

• Bit 18 (OV)

The following bits in the MASK1 register work with the status bits

in the IPEAK and VPEAK registers, respectively:

• Bit 23 (PKI)

• Bit 24 (PKV)

Data Sheet

The following bits in the MASK0 register work with the status bits

in the PHSIGN register:

• Bits[6:8] (REVAPx)

• Bits[10:12] (REVRPx)

• Bit 9, Bit 13, and Bit 18 (REVPSUMx)

When the STATUSx register is read and one of these bits is set

to 1, the status register associated with the bit is immediately

read to identify the phase that triggered the interrupt and only

at that time can the STATUSx register be written back with the bit

set to 1.

Using the Interrupts with an MCU

Figure 98 shows a timing diagram that illustrates a suggested

implementation of the ADE7880 interrupt management using an

MCU. At Time t1, the IRQx pin goes active low indicating that

one or more interrupt events have occurred in the ADE7880, at

which point the following steps should be taken:

1. Tie the IRQx pin to a negative-edge-triggered external

interrupt on the MCU.

2. On detection of the negative edge, configure the MCU to

start executing its interrupt service routine (ISR).

3. On entering the ISR, disable all interrupts using the global

interrupt mask bit. At this point, the MCU external

interrupt flag can be cleared to capture interrupt events

that occur during the current ISR.

4. When the MCU interrupt flag is cleared, a read from

STATUSx, the interrupt status register, is carried out. The

interrupt status register content is used to determine the

source of the interrupt(s) and, hence, the appropriate

action to be taken.

5. The same STATUSx content is written back into the

ADE7880 to clear the status flag(s) and reset the IRQx line

to logic high (t2).

If a subsequent interrupt event occurs during the ISR (t3), that

event is recorded by the MCU external interrupt flag being

set again.

On returning from the ISR, the global interrupt mask bit is

cleared (same instruction cycle) and the external interrupt flag

uses the MCU to jump to its ISR once again. This ensures that

the MCU does not miss any external interrupts.

Figure 99 shows a recommended timing diagram when the

status bits in the STATUSx registers work in conjunction with

bits in other registers. When the IRQx pin goes active low, the

STATUSx register is read, and if one of these bits is 1, a second

status register is read immediately to identify the phase that

triggered the interrupt. The name, PHx, in Figure 99 denotes

one of the PHSTATUS, IPEAK, VPEAK, or PHSIGN registers.

Then, STATUSx is written back to clear the status flag(s).

Rev. A | Page 72 of 104

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