ADE7880ACPZ-RL(RevA) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADE7880ACPZ-RL
(Rev.:RevA)

Polyphase Multifunction Energy Metering IC with Harmonic Monitoring

Analog Devices 

ADE7880

Data Sheet

I2C-Compatible Interface

The ADE7880 supports a fully licensed I2C interface. The I2C

interface is implemented as a full hardware slave. SDA is the

data I/O pin, and SCL is the serial clock. These two pins are

shared with the MOSI and SCLK pins of the on-chip SPI

interface. The maximum serial clock frequency supported by this

interface is 400 kHz.

The two pins used for data transfer, SDA and SCL, are configured

in a wire-AND’ed format that allows arbitration in a multimaster

system.

The transfer sequence of an I2C system consists of a master device

initiating a transfer by generating a start condition while the bus

is idle. The master transmits the address of the slave device and

the direction of the data transfer in the initial address transfer. If

the slave acknowledges, the data transfer is initiated. This

continues until the master issues a stop condition, and the bus

becomes idle.

I2C Write Operation

The write operation using the I2C interface of the ADE7880

initiate when the master generates a start condition and consists

in one byte representing the address of the ADE7880 followed

by the 16-bit address of the target register and by the value of

the register.

The most significant seven bits of the address byte constitute

the address of the ADE7880 and they are equal to 0111000b.

Bit 0 of the address byte is a read/write bit. Because this is a

write operation, it has to be cleared to 0; therefore, the first byte

of the write operation is 0x70. After every byte is received, the

ADE7880 generates an acknowledge. As registers can have 8, 16,

or 32 bits, after the last bit of the register is transmitted and the

ADE7880 acknowledges the transfer, the master generates a

stop condition. The addresses and the register content are sent

with the most significant bit first. See Figure 100 for details of

the I2C write operation.

15

S01110000

87

0 31

24 23

16 15

87

0

S

SLAVE ADDRESS

MOST SIGNIFICANT

8 BITS OF REGISTER

ADDRESS

LESS SIGNIFICANT

8 BITS OF REGISTER

ADDRESS

BYTE 3 (MOST

SIGNIFICANT)

OF REGISTER

BYTE 2 OF REGISTER BYTE 1 OF REGISTER

BYTE 0 (LESS

SIGNIFICANT) OF

REGISTER

ACK GENERATED

BY ADE7880

Figure 100. I2C Write Operation of a 32-Bit Register

Rev. A | Page 74 of 104

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