ADP2370CPZ-REDYKIT(RevA) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADP2370CPZ-REDYKIT
(Rev.:RevA)

High Voltage, 1.2 MHz/600 kHz, 800 mA, Low Quiescent Current Buck Regulator

Analog Devices 

Data Sheet

ADP2370/ADP2371

100% DUTY CYCLE

The ADP2370/ADP2371 enter and exit 100% duty cycle smoothly.

The control loop seeks the next clock cycle while the high-side

switch is engaged. When this occurs, the clock signal is masked

and the PMOS remains on. When the input voltage increases, the

internal VCOMP node decreases its signal to the control loop; thus,

the device stops skipping clock cycles and exits 100% duty cycle.

VIN

1

VOUT

2

If the device is synchronized to an external clock, the PSM

mode is disabled and the device stays in forced PWM mode.

Connect FSEL to ground when synchronizing to a frequency

range from 400 kHz to 800 kHz, and connect FSEL to the input

voltage when the external frequency is in the range of 800 kHz

to 1600 kHz. FSEL has an internal pull-down resistor and

defaults to the 600 kHz mode when FSEL is unconnected.

INTERNAL 1.2MHZ

1 23 4

INTERNAL 600kHZ

SYNC

PWM CLOCK (IF FSEL = 1)

3

INDUCTOR CURRENT

CH1 1.00V BW CH2 1.00V BW M2.00ms A CH1

CH3 50.0mA Ω BW

T 32.20%

4.90V

Figure 74. Transition into and out of Dropout in PSM Mode,

VOUT = 5 V, 100 mA Load

PWM CLOCK (IF FSEL = 0)

PWM CLOCK FOLLOWS SYNC UNTIL IT MISSES

4 × 1.2MHZ INTERNAL CLOCK CYCLES

Figure 76. Typical SYNC Timing

SW

VIN

VOUT

1

VOUT

2

INDUCTOR CURRENT

3

INDUCTOR CURRENT

123

CH1 1.00V BW CH2 1.00V BW M2.00ms A CH1

CH3 50.0mA Ω BW

T 32.20%

4.90V

Figure 75. Transition into and out of Dropout in PWM Mode,

VOUT = 5 V, 100 mA Load

SYNCHRONIZING

It is possible to synchronize the ADP2370/ADP2371 to an external

clock within a frequency range from 400 kHz to 1.6 MHz. The

device automatically detects the rising edge of the first clock

and synchronizes to the external clock. When the clock signal

stops, the device automatically switches back to the internal

clock and continues operating.

The switchover is initiated when no rising edge on the SYNC

pin can be detected on the internal clock for a duration of four

clock cycles. Therefore, the maximum delay time can be 6.7 µs if

the internal clock is running at its minimum frequency of 600 kHz.

During this time, there is no clock signal available. The output

stops switching until the ADP2370 circuitry switches to the

internal clock signal.

SYNC

4

CH1 5.00V BW CH2 100mV BW M20.0µs A CH4

CH3 200mA Ω BW CH4 5.00V BW T 20.0%

2.00V

Figure 77. Typical SYNC Transient, 1.2 MHz to 800 kHz to 1.2 MHz

SW

1

VOUT

2

INDUCTOR CURRENT

3

SYNC

4

CH1 5.00V BW CH2 50.0mV BW M20.0µs A CH4

CH3 200mA Ω BW CH4 5.00V BW T 20.0%

2.00V

Figure 78. SYNC Transient 1.2 MHz to 800 kHz

Rev. A | Page 23 of 32

Share Link: