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DESCRIPTION OF SERIAL REGISTERS
ADS6445, ADS6444
ADS6443, ADS6442
SLAS531 – MAY 2007
Table 13. Serial Register A
REGISTER
ADDRESS
BITS
A4 - A0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
00
<RST>
S/W RESET
0
0
0
0
<REF>
INTERNAL
OR
EXTERNAL
<PDN CHD>
POWER
DOWN CH D
<PDN CHC>
POWER
DOWN CHC
<PDN CHB> <PDN CHA>
POWER
POWER
DOWN CH B DOWN CH A
<PDN>
GLOBAL
POWER
DOWN
D0 - D4
D0
0
1
D1
0
1
D2
0
1
D3
0
1
D4
0
1
D5
0
1
D10
1
Power down modes
<PDN GLOBAL>
Normal operation
Global power down, including all channels ADCs, internal references, internal PLL and output
buffers
<PDN CHA>
CH A Powered up
CH A ADC Powered down
<PDN CHB>
CH B Powered up
CH B ADC Powered down
<PDN CHC>
CH C Powered up
CH C ADC Powered down
<PDN CHD>
CH D Powered up
CH D ADC Powered down
<REF> Reference
Internal reference enabled
External reference enabled
<RST>
Software reset applied – resets all internal registers and self-clears to 0
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