ADS6445, ADS6444
ADS6443, ADS6442
SLAS531 – MAY 2007
www.ti.com
Table 14. Serial Register B
REGISTER
ADDRESS
BITS
A4 - A0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
04
0
0
0
0
<CLKIN GAIN>
INPUT CLOCK BUFFER GAIN CONTROL
0
0
D6 - D2
11000
00000
01100
01010
01001
01000
<CLKIN GAIN> Input clock buffer gain control
Gain 0, minimum gain
Gain 1, default gain after reset
Gain 2
Gain 3
Gain 4
Gain 5, maximum gain
Table 15. Serial Register C
REGISTER
ADDRESS
BITS
A4 - A0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
<DF>
DATA
00
0
DORMAT 2S
COMP OR
0
STRAIGHT
BINARY
<PATTERNS>
TEST PATTERNS
0
0
0
0
0
D7 - D5
000
001
010
011
100
101
110
111
D9
0
1
<PATTERNS> Capture test patterns
Normal ADC operation
Output all zeros
Output all ones
Output toggle pattern
Unused
Output custom pattern (contents of CUSTOM pattern registers 0x0B and 0x0C)
Output DESKEW pattern (serial stream of 1010..)
Output SYNC pattern
<DF> Data format selection
2s Complement format
Straight binary format
22
Submit Documentation Feedback