ADS6422 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ADS6422

QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS

STMicroelectronics 

ADS6445, ADS6444

ADS6443, ADS6442

SLAS531 – MAY 2007

www.ti.com

D5

<COARSE GAIN>Coarse gain control

0

0 dB Coarse gain (full-scale range = 2.0 VPP)

1

3.5dB Coarse gain (full-scale range = 1.34 VPP)

D6

MSB or LSB First selection

0

MSB First

1

LSB First

D7

Byte/bit wise outputs (only when 2-wire is selected)

0

Byte wise

1

Bit wise

D10

<OVRD> Over-ride bit. All the functions in register 0x0D can also be controlled using the

parallel control pins. By setting bit <OVRD> = 1, the contents of register 0x0D will over-ride

the settings of the parallel pins.

0

Disable over-ride

1

Enable over-ride

Table 19. Serial Register G

REGISTER

ADDRESS

A4 - A0

10

D10

D9

D8

D7

D6

<TERM CLK>

LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS

BITS

D5

D4

D3

D2

<LVDS CURR>

LVDS CURRENT SETTINGS

D1

D0

<LVDS DOUBLE>

LVDS CURRENT DOUBLE

D0

0

1

D1

0

1

D3-D2

00

01

10

11

D5-D4

00

01

10

11

D10-D6

00000

00001

<CURR DOUBLE> LVDS current double for data outputs

Nominal LVDS current, as set by <D5…D2>

Double the nominal value

<CURR DOUBLE> LVDS current double for bit and word clock outputs

Nominal LVDS current, as set by <D5…D2>

Double the nominal value

<LVDS CURR> LVDS current setting for data outputs

3.5 mA

4 mA

2.5 mA

3 mA

<LVDS CURR> LVDS current setting for bit and word clock outputs

3.5 mA

4 mA

2.5 mA

3 mA

<TERM CLK> LVDS internal termination for bit and word clock outputs

No internal termination

166 Ω

24

Submit Documentation Feedback

Share Link: