ADS6422 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADS6422 Datasheet PDF : 75 Pages
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ADS6445, ADS6444
ADS6443, ADS6442
SLAS531 – MAY 2007
www.ti.com
PIN ASSIGNMENTS (1-WIRE INTERFACE) (continued)
NAME
PINS
INA_P, INA_M
NO.
12,11
INB_P, INB_M
15,14
INC_P, INC_M
34,35
IND_P, IND_M
CAP
37,38
5
SCLK
44
SDATA
43
SEN
42
RESET
6
PDN
41
CFG1
30
CFG2
CFG3
CFG4
VCM
OUTPUT PINS
DA_P,DA_M
DB_P,DB_M
DC_P,DC_M
DD_P,DD_M
DCLKP,DCLKM
FCLKP,FCLKM
UNUSED
NC
PAD
29
28
21
22
62,63
60,61
52,53
50,51
57,58
55,56
1-4,45-48
20
0
I/O
NO. OF
PINS
DESCRIPTION
I
2
Differential input signal pair, channel A. If unused, the pins should be tied to VCM. Do
not float.
I
2
Differential input signal pair, channel B.If unused, the pins should be tied to VCM. Do
not float.
I
2
Differential input signal pair, channel C. If unused, the pins should be tied to VCM.
Do not float.
I
2
Differential input signal pair, channel D. If unused, the pins should be tied to VCM.
Do not float.
1 Connect 2-nF capacitance from pin to ground
This pin functions as serial interface clock input when RESET is low.
I
1
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN
modes (along with SDATA). Refer to Table 5 for description.
This pin has an internal pull-down resistor.
This pin functions as serial interface data input when RESET is low.
I
1
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN
modes (along with SCLK). Refer to Table 5 for description.
This pin has an internal pull-down resistor.
This pin functions as serial interface enable input when RESET is low.
I
1
When RESET is high, it controls coarse gain and internal/external reference modes.
Refer to Table 6 for description.
This pin has an internal pull-up resistor.
Serial interface reset input.
When using the serial interface mode, the user MUST initialize internal registers
through hardware RESET by applying a high-going pulse on this pin or by using
I
1 software reset option. Refer to the Serial Interface section. In parallel interface mode,
tie RESET permanently high. (SCLK, SDATA and SEN function as parallel control
pins in this mode).
The pin has an internal pull-down resistor to ground.
I
1 Global power down control pin.
Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock
I
1 selection. Refer to Table 8 for description.
Tie to ground for 1-wire interface with DDR bit clock.
Parallel input pin. It controls 14x or 16x serialization and SDR bit clock capture edge.
I
1 Refer to Table 9 for description.
For 14x serialization with DDR bit clock, tie to ground or AVDD.
I
1 RESERVED pin - Tie to ground.
I
1
Parallel input pin. It controls data format and MSB or LSB first modes. Refer to
Table 11 for description.
Internal reference mode – common-mode voltage output
I/O
1 External reference mode – reference input. The voltage forced on this pin sets the
internal reference.
O
2 Channel A differential LVDS data output pair
O
2 Channel B differential LVDS data output pair
O
2 Channel C differential LVDS data output pair
O
2 Channel D differential LVDS data output pair
O
2 Differential bit clock output pair
O
2 Differential frame clock output pair
8 These pins are unused in the 1-wire interface. Do not connect
1 Do not connect
1
Connect to ground plane using multiple vias. Refer to Board Design Considerations
in the application section.
30
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