ADS6444IRGCT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ADS6444IRGCT

QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS

STMicroelectronics 

ADS6445, ADS6444

ADS6443, ADS6442

SLAS531 – MAY 2007

www.ti.com

OUTPUT BIT ORDER

In the 2-wire interface, three types of bit order are supported - byte-wise, bit-wise and word-wise.

Byte-wise: Each 14-bit sample is split across the 2 wires. Wires DA0, DB0, DC0 and DD0 carry the 7 LSB bits

D6 - D0 and wires DA1, DB1, DC1 and DD1 carry the 7 MSB bits.

Bit-wise: Each 14-bit sample is split across the 2 wires. Wires DA0, DB0, DC0 and DD0 carry the 7 even bits

(D0,D2,D4..) and wires DA1, DB1, DC1 and DD1 carry the 7 odd bits (D1,D3,D5...).

Word-wise: In this case, all 14-bits of a sample are sent over a single wire. Successive samples are sent over

the 2 wires. For example sample N is sent on wires DA0, DB0, DC0 and DD0, while sample N+1 is sent over

wires DA1, DB1, DC1 and DD1. The frame clock frequency is 0.5x sampling frequency, with the rising edge

aligned with the start of each word.

MSB/LSB FIRST

By default after reset, the 14-bit ADC data is output serially with the MSB first (D13, D12, D11,...D1,D0). The

data can be output LSB first also by programming the register bit <MSB_LSB_First>. In the 2-wire mode, the bit

order in each wire is flipped in the LSB first mode.

OUTPUT DATA FORMATS

Two output data formats are supported – 2s complement (default after reset) and offset binary. They can be

selected using the serial interface register bit <DF>. In the event of an input voltage overdrive, the digital outputs

go to the appropriate full-scale level. For a positive overdrive, the output code is 0x3FFF in offset binary output

format, and 0x1FFF in 2s complement output format. For a negative input overdrive, the output code is 0x0000

in offset binary output format and 0x2000 in 2s complement output format.

LVDS CURRENT CONTROL

The default LVDS buffer current is 3.5 mA. With an external 100-Ω termination resistance, this develops

±350-mV logic levels at the receiver. The LVDS buffer currents can also be programmed to 2.5 mA, 3.0 mA and

4.5 mA using the register bits <LVDS CURR>. In addition, there exists a current double mode, where the LVDS

nominal current is doubled (register bits <CURR DOUBLE>, refer to Table 19).

LVDS INTERNAL TERMINATION

An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially

terminated inside the device. Five termination resistances are available – 166, 200, 250, 333, and 500 Ω

(nominal with ±20% variation). Any combination of these terminations can be programmed; the effective

termination will be the parallel combination of the selected resistances. The terminations can be programmed

separately for the clock and data buffers (bits <TERM CLK> and <TERM DATA>, refer to Table 20).

The internal termination helps to absorb any reflections from the receiver end, improving the signal integrity. This

makes it possible to drive up to 10 pF of load capacitance, compared to only 5 pF without the internal

termination. Figure 97 and Figure 98 show the eye diagram with 5 pF and 10 pF load capacitors (connected

from each output pin to ground).

With 100-Ω internal and 100-Ω external termination, the voltage swing at the receiver end will be halved

(compared to no internal termination). The voltage swing can be restored by using the LVDS current double

mode (bits <CURR DOUBLE>, refer to Table 19).

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