ADS6445, ADS6444
ADS6443, ADS6442
SLAS531 – MAY 2007
Table 30. Timings for 2-Wire Interface, SDR Bit Clock
SAMPLING
SERIALIZATION FREQUENCY
DATA SETUP TIME, tsu
ns
DATA HOLD TIME, th
ns
MSPS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
65
0.8
1
1
1.2
40
1.5
1.7
1.6
1.8
3.4
14×
20
3.4
3.6
3.3
3.5
10
6.9
7.2
6.6
6.9
3.7
65
0.65
0.85
0.8
1.0
40
1.3
1.5
1.4
1.6
3.4
16×
20
2.8
3.0
2.8
3.0
10
6.0
6.3
5.8
6.1
3.7
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tdelay
ns
TYP
Fs ≥ 40 MSPS
4.4
Fs < 40 MSPS
5.2
Fs ≥ 40 MSPS
4.4
Fs < 40 MSPS
5.2
MAX
5.4
6.7
5.4
6.7
SAMPLING FREQUENCY
MSPS
≥ 65
Table 31. Output Jitter (applies to all interface options)
BIT CLOCK JITTER, CYCLE-CYCLE
ps, peak-peak
MIN
TYP
MAX
350
FRAME CLOCK JITTER, CYCLE-CYCLE
ps, peak-peak
MIN
TYP
MAX
75
66
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