ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Core Timer
The following timing specification applies to FLAG3 when it is
configured as the core timer (CTIMER).
Table 16. Core Timer
Parameter
Switching Characteristic
tWCTIM
CTIMER Pulse Width
Min
2 × tPCLK – 1
Max
Unit
ns
FLAG3
(CTIMER)
tW CT IM
Figure 12. Core Timer
Timer PWM_OUT Cycle Timing
The following timing specification applies to Timer0, Timer1,
and Timer2 in PWM_OUT (pulse-width modulation) mode.
Timer signals are routed to the DAI_P20–1 pins through the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
Table 17. Timer PWM_OUT Timing
Parameter
Switching Characteristic
tPWMO
Timer Pulse Width Output
Min
2 tPCLK – 1
Max
2(231 – 1) tPCLK
Unit
ns
DAI_P20-1
(TIMER2-0)
tPWMO
Figure 13. Timer PWM_OUT Timing
Rev. A | Page 22 of 52 | December 2006