ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
ALE
RD
tALEW
tALERW
tRRH
tRW
tRWALE
tRDDRV
WR
AD15-8
tADAS
tADAH
VALID ADDRESS
tDAWH
VALID ADDRESS
AD7-0
VALID ADDRESS
tALEHZ
VALID
DATA
NOTE: MEMORY READS ALWAYS OCCUR IN GROUPS OF FOUR
BETWEEN ALE CYCLES. THIS FIGURE ONLY SHOWS TWO MEMORY
READS IN ORDER TO PROVIDE THE NECESSARY TIMING INFORMATION.
tADRH
VALID ADDRESS
tDAD tDRS tDRH
VALID
DATA
VALID
ADDRESS
VALID
ADDRESS
Figure 18. Read Cycle for 8-Bit Memory Timing
Rev. A | Page 27 of 52 | December 2006