ADSP-21363(RevA) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-21363
(Rev.:RevA)

SHARC® Processor

Analog Devices 

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Sample Rate Converter—Serial Output Port

For the serial output port, the frame-sync is an input and should

meet setup and hold times with regard to SCLK on the output

port. The serial data output, SDATA, has a hold time and delay

specification with regard to SCLK. Note that SCLK rising edge is

the sampling edge and the falling edge is the drive edge.

Table 34. SRC, Serial Output Port

Parameter

Timing Requirements

tSRCSFS1

tSRCHFS1

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

Min

Max

Unit

3

ns

3

ns

Switching Characteristics

tSRCTDD1

tSRCTDH1

Transmit Data Delay After SCLK Falling Edge

Transmit Data Hold After SCLK Falling Edge

10.5

ns

2

ns

1 DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(SDATA)

SAMPLE EDGE

tSRCCLK

tSRCCLKW

tSRCSFS

tSRCHFS

tSRCTDD

tSRCTDH

Figure 28. SRC Serial Output Port Timing

Rev. A | Page 37 of 52 | December 2006

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