AOZ1034DI View Datasheet(PDF) - Alpha and Omega Semiconductor
Part Name
Description
Manufacturer
AOZ1034DI Datasheet PDF : 18 Pages
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AOZ1034
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck
converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
ΔVO
=
ΔIL
×
⎛
⎝
ES
RCO
+
-8----×-----f--1-×-----C-----O--⎠⎞
where;
CO is output capacitor value, and
ESRCO is the Equivalent Series Resistor of output capacitor.
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
ΔVO
=
ΔIL
×
------------1-------------
8 × f × CO
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
ΔVO = ΔIL × ESRCO
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum are recommended
to be used as output capacitors.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current.
It can be calculated by:
ICO_RMS = --Δ----I--L--
12
Usually, the ripple current rating of the output capacitor
is a smaller issue because of the low current stress.
When the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be
overstressed.
External Schottky Diode for High Input Operation
When VIN is higher than 16V, an external 1A schottky
diode is required between LX and PGND for proper
operation.
Loop Compensation
The AOZ1034 employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole can be
calculated by:
fP1
=
----------------1------------------
2π × CO × RL
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
fZ1
=
-----------------------1-------------------------
2π × CO × ESRCO
where;
CO is the output filter capacitor,
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
The compensation design is actually to shape the
converter control loop transfer function to get desired
gain and phase. Several different types of compensation
network can be used for the AOZ1034. For most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ1034, FB pin and COMP pin are the inverting
input and the output of internal error amplifier. A series
R and C compensation network connected to COMP
provides one pole and one zero. The pole is:
fP2
=
----------------G-----E----A-----------------
2π × CC × GVEA
where;
GEA is the error amplifier transconductance, which is
200 x 10-6 A/V,
GVEA is the error amplifier voltage gain, which is 500 V/V, and
CC is compensation capacitor in Figure 1.
The zero given by the external compensation network,
capacitor CC and resistor RC, is located at:
fZ2
=
-----------------1------------------
2π × CC × RC
Rev. 1.1 September 2010
www.aosmd.com
Page 10 of 18
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