4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Figure 23. ICC Test Condition, Active Mode
VCC
ICC
VCC
VCC
P0
VCC
RST EA
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
Figure 24. ICC Test Condition, Idle Mode
VCC
ICC
VCC
VCC
P0
All other pins are disconnected.
(NC)
CLOCK
SIGNAL
RST EA
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 25. ICC Test Condition, Power-down Mode
VCC
ICC
VCC
VCC
P0
RST EA
(NC)
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 26. Clock Signal Waveform for ICC Tests in Active and Idle Modes
VCC-0.5V
0.45V
TCHCL
TCLCH
TCLCH = TCHCL = 5ns.
0.7VCC
0.2VCC-0.1
69