AT80C51RD2/AT83C51Rx2
External Data Memory Read Cycle
ALE
PSEN
RD
PORT 0
PORT 2
ADDRESS
OR SFR-P2
TLLDV
TWHLH
TLLWL
TRLRH
TLLAX
A0-A7
TAVWL
TAVDV
TRLAZ
TRHDX
DATA IN
ADDRESS A8-A15 OR SFR P2
TRHDZ
Serial Port Timing - Shift
Register Mode
Table 54. Symbol Description
Symbol
TXLXL
TQVHX
TXHQX
TXHDX
TXHDV
Parameter
Serial port clock cycle time
Output data set-up to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
Table 55. AC Parameters for a Fix Clock
Symbol
TXLXL
TQVHX
TXHQX
TXHDX
TXHDV
-M
Min
300
200
30
0
Max
Min
300
200
30
0
117
-L
Max
117
Units
ns
ns
ns
ns
ns
Table 56. AC Parameters for a Variable Clock
Symbol
TXLXL
TQVHX
TXHQX
TXHDX
TXHDV
Type
Min
Min
Min
Min
Max
Standard
X Parameter for - X Parameter for -L
Clock X2 Clock
M Range
Range
12 T
6T
10 T - x
5T-x
50
50
2T-x
T-x
20
20
x
x
0
0
10 T - x
5 T- x
133
133
Units
ns
ns
ns
ns
ns
75
4113B–8051–03/05