Shift Register Timing Waveforms
INSTRUCTION
ALE
CLOCK
OUTPUT DATA
WRITE to SBUF
INPUT DATA
CLEAR RI
0
1
2
3
TXLXL
TQVXH
TXHQX
0
1
2
TXHDV
VALID
TXHDX
VALID
VALID
4
3
VALID
5
4
VALID
6
5
VALID
7
8
6
7
SET TI
VALID
VALID
SET RI
External Clock Drive Waveforms
VCC-0.5V
0.45V
0.7VCC
0.2VCC-0.1
TCHCL
AC Testing Input/Output Waveforms
TCLCX
TCLCL
TCHCX
TCLCH
Float Waveforms
Clock Waveforms
INPUT/OUTPUT
VCC -0.5V
0.45V
0.2 VCC + 0.9
0.2 VCC - 0.1
AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”.
Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”.
FLOAT
VOH - 0.1 V
VOL + 0.1 V
VLOAD
VLOAD + 0.1 V
VLOAD - 0.1 V
For timing purposes as port pin is no longer floating when a 100 mV changes from load
voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level
occurs. IOL/IOH ≥ ± 20 mA.
Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
76 AT80C51RD2/AT83C51Rx2
4113B–8051–03/05