TS80C31X2-LIB View Datasheet(PDF) - Atmel Corporation
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Description
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TS80C31X2-LIB Datasheet PDF : 42 Pages
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14.5.4 External Data Memory Read Cycle
ALE
PSEN
RD
PORT 0
PORT 2
ADDRESS
OR SFR-P2
TLLDV
TWHLH
TLLWL
TRLDV
TRLRH
TLLAX
A0-A7
TAVWL
TAVDV
TRLAZ
TRHDX
DATA IN
ADDRESS A8-A15 OR SFR P2
TRHDZ
TXLXL
TQVHX
TXHQX
TXHDX
TXHDV
Speed
Symbol
TXLXL
TQVHX
TXHQX
TXHDX
TXHDV
Figure 14-8. External Data Memory Read Cycle
Table 14-11. Serial Port Timing - Shift Register Mode
Symbol
Parameter
Serial port clock cycle time
Output data set-up to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
Table 14-12. AC Parameters for a Fix Clock
-M
40 MHz
Min
Max
300
200
30
0
117
-V
X2 mode
30 MHz
60 MHz equiv.
Min
Max
200
117
13
0
34
-V
standard mode 40
MHz
Min
Max
300
200
30
0
117
-L
X2 mode
20 MHz
40 MHz equiv.
Min
Max
300
200
30
0
117
-L
standard mode
30 MHz
Min
Max
400
283
47
0
200
Units
ns
ns
ns
ns
ns
36 AT/TS80C31X2
4428D–8051–08/05
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