14.5.6 External Clock Drive Waveforms
VCC-0.5 V
0.45 V
0.7VCC
0.2VCC-0.1 V
TCHCL
TCLCX
TCHCX
TCLCH
TCLCL
14.5.7
Figure 14-10. External Clock Drive Waveforms
AC Testing Input/Output Waveforms
INPUT/OUTPUT
VCC-0.5 V
0.45 V
0.2VCC+0.9
0.2VCC-0.1
14.5.8
Figure 14-11. AC Testing Input/Output Waveforms
AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing
measurement are made at VIH min for a logic “1” and VIL max for a logic “0”.
Float Waveforms
FLOAT
VOH-0.1 V VLOAD
VOL+0.1 V
VLOAD+0.1 V
VLOAD-0.1 V
Figure 14-12. Float Waveforms
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH
≥ ± 20mA.
14.5.9
Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by
two.
38 AT/TS80C31X2
4428D–8051–08/05