AT87F51RC-12PC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
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AT87F51RC-12PC Datasheet PDF : 25 Pages
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AT87F51RC
Program Memory Lock Bits
The AT87F51RC has three lock bits that can be left unpro-
grammed (U) or can be programmed (P) to obtain the addi-
tional features listed in the following table.
Table 8. Lock Bit Protection Modes
Program Lock Bits
LB1 LB2 LB3 Protection Type
1
U
U
U No program lock features.
MOVC instructions executed
from external program
memory are disabled from
fetching code bytes from
2
P
U
U internal memory, EA is
sampled and latched on reset,
and further programming of
the QuickFlash memory is
disabled.
3
P
P
U
Same as mode 2, but verify is
also disabled.
4
P
P
P
Same as mode 3, but external
execution is also disabled.
When lock bit 1 is programmed, the logic level at the EA pin
is sampled and latched during reset. If the device is pow-
ered up without a reset, the latch initializes to a random
value and holds that value until reset is activated. The
latched value of EA must agree with the current logic level
at that pin in order for the device to function properly.
Programming the QuickFlash
The AT87F51RC is shipped with the on-chip QuickFlash
memory array ready to be programmed. The programming
interface needs a high-voltage (12-volt) program enable
signal and is compatible with conventional third-party Flash
or EPROM programmers.
The AT87F51RC code memory array is programmed byte-
by-byte.
Programming Algorithm: Before programming the
AT87F51RC, the address, data, and control signals should
be set up according to the QuickFlash programming mode
table and Figure 10 and Figure 11. To program the
AT87F51RC, take the following steps:
1. Input the desired memory location on the address
lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V.
5. Pulse ALE/PROG once to program a byte in the
QuickFlash array or the lock bits. The byte-write
cycle is self-timed and typically takes no more than
50 µs. Repeat steps 1 through 5, changing the
address and data for the entire array or until the end
of the object file is reached.
Data Polling: The AT87F51RC features Data Polling to
indicate the end of a write cycle. During a write cycle, an
attempted read of the last byte written will result in the com-
plement of the written data on P0.7. Once the write cycle
has been completed, true data is valid on all outputs, and
the next cycle may begin. Data Polling may begin any time
after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can also
be monitored by the RDY/BSY output signal. P3.0 is pulled
low after ALE goes high during programming to indicate
BUSY. P3.0 is pulled high again when programming is
done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been
programmed, the programmed code data can be read back
via the address and data lines for verification. The lock bits
cannot be verified directly. Verification of the lock bits is
achieved by observing that their features are enabled.
Reading the Signature Bytes: The signature bytes are
read by the same procedure as a normal verification of
locations 000H, 100H, and 200H, except that P3.6 and
P3.7 must be pulled to a logic low. The values returned are
as follows.
(000H) = 1EH indicates manufactured by Atmel
(100H) = 87H indicates 87F family
(200H) = 07H indicates 87F51RC
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