ATMEGA64L-8MI View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATMEGA64L-8MI

8-bit AVR® Microcontroller with 64K Bytes In-System Programmable Flash

Atmel Corporation 

Timer/Counter Timing

Diagrams

between OCR0 and TCNT0 when the counter decrements. The PWM frequency for the

output when using phase correct PWM can be calculated by the following equation:

fOCnPCPWM

=

-f--c---l-k--_---I-/-O---

N ⋅ 510

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR0 Register represent special cases when generating a

PWM waveform output in the phase correct PWM mode. If the OCR0 is set equal to

BOTTOM, the output will be continuously low and if set equal to MAX the output will be

continuously high for non-inverted PWM mode. For inverted PWM the output will have

the opposite logic values.

At the very start of period 2 in Figure 40 OCn has a transition from high to low even

though there is no Compare Match. The point of this transition is to guarantee symmetry

around BOTTOM. There are two cases that give a transition without Compare Match.

• OCR0 changes its value from MAX, like in Figure 40. When the OCR0 value is MAX

the OCn pin value is the same as the result of a down-counting Compare Match. To

ensure symmetry around BOTTOM the OCn value at MAX must correspond to the

result of an up-counting Compare Match.

• The timer starts counting from a higher value than the one in OCR0, and for that

reason misses the Compare Match and hence the OCn change that would have

happened on the way up.

Figure 41 and Figure 42 contain timing data for the Timer/Counter operation. The

Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as

a clock enable signal. The figure shows the count sequence close to the MAX value.

Figure 43 and Figure 44 show the same timing data, but with the prescaler enabled. The

figures illustrate when interrupt flags are set.

The following figures show the Timer/Counter in synchronous mode, and the timer clock

(clkT0) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should

be replaced by the Timer/Counter Oscillator clock. The figures include information on

when interrupt flags are set. Figure 41 contains timing data for basic Timer/Counter

operation. The figure shows the count sequence close to the MAX value in all modes

other than phase correct PWM mode.

Figure 41. Timer/Counter Timing Diagram, no Prescaling

clkI/O

clkTn

(clkI/O/1)

TCNTn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

TOVn

Figure 42 shows the same timing data, but with the prescaler enabled.

100 ATmega64(L)

2490G–AVR–03/04

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