ATMEGA64L-8MI View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATMEGA64L-8MI

8-bit AVR® Microcontroller with 64K Bytes In-System Programmable Flash

Atmel Corporation 

extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and

“CBR”.

The assembly code example returns the TCNTn value in the r17:r16 register pair.

It is important to notice that accessing 16-bit registers are atomic operations. If an inter-

rupt occurs between the two instructions accessing the 16-bit register, and the interrupt

code updates the temporary register by accessing the same or any other of the 16-bit

timer registers, then the result of the access outside the interrupt will be corrupted.

Therefore, when both the main code and the interrupt code update the temporary regis-

ter, the main code must disable the interrupts during the 16-bit access.

The following code examples show how to do an atomic read of the TCNTn Register

contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the

same principle.

Assembly Code Example(1)

TIM16_ReadTCNTn:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Read TCNTn into r17:r16

in r16,TCNTnL

in r17,TCNTnH

; Restore global interrupt flag

out SREG,r18

ret

C Code Example(1)

unsigned int TIM16_ReadTCNTn( void )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Read TCNTn into i */

i = TCNTn;

/* Restore global interrupt flag */

SREG = sreg;

return i;

}

Note:

1. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,

and “SBI” instructions must be replaced with instructions that allow access to

extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and

“CBR”.

The assembly code example returns the TCNTn value in the r17:r16 register pair.

114 ATmega64(L)

2490G–AVR–03/04

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