ATMEGA64L-8MI View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATMEGA64L-8MI

8-bit AVR® Microcontroller with 64K Bytes In-System Programmable Flash

Atmel Corporation 

Figure 128. General Port Pin Schematic Diagram

See Boundary-scan Description

for Details!

PUExn

OCxn

PUD

QD

DDxn

Q CLR

RESET

WDx

RDx

Pxn

IDxn

ODxn

SLEEP

QD

PORTxn

Q CLR

RESET

WPx

RRx

SYNCHRONIZER

DQ

LQ

DQ

PINxn

Q

RPx

CLK I/O

PUD:

PUExn:

OCxn:

ODxn:

IDxn:

SLEEP:

PULLUP DISABLE

PULLUP ENABLE for pin Pxn

OUTPUT CONTROL for pin Pxn

OUTPUT DATA to pin Pxn

INPUT DATA from pin Pxn

SLEEP CONTROL

WDx:

RDx:

WPx:

RRx:

RPx:

CLK I/O :

WRITE DDRx

READ DDRx

WRITE PORTx

READ PORTx REGISTER

READ PORTx PIN

I/O CLOCK

Boundary-scan and the Two-

wire Interface

The two Two-wire Interface pins SCL and SDA have one additional control signal in the

scan-chain; Two-wire Interface Enable – TWIEN. As shown in Figure 129, the TWIEN

signal enables a tri-state buffer with slew-rate control in parallel with the ordinary digital

port pins. A general scan cell as shown in Figure 133 is attached to the TWIEN signal.

Notes:

1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordi-

nary scan support for digital port pins suffice for connectivity tests. The only reason

for having TWIEN in the scan path, is to be able to disconnect the slew-rate control

buffer when doing boundary-scan.

2. Make sure the OC and TWIEN signals are not asserted simultaneously, as this will

lead to drive contention.

260 ATmega64(L)

2490G–AVR–03/04

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