ATmega64(L)
Figure 129. Additional Scan Signal for the Two-wire Interface
PUExn
Scanning the RESET Pin
OCxn
ODxn
Pxn
TWIEN
SRC
Slew-rate limited
IDxn
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active
high logic for High Voltage Parallel programming. An observe-only cell as shown in Fig-
ure 130 is inserted both for the 5V reset signal; RSTT, and the 12V reset signal;
RSTHV.
Figure 130. Observe-only Cell
ShiftDR
To
Next
Cell
FF1
0
DQ
1
2490G–AVR–03/04
From
Previous
Cell
ClockDR
261