ATMEGA64L-8MI View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATMEGA64L-8MI
Atmel Corporation
ATMEGA64L-8MI Datasheet PDF : 363 Pages
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ATmega64(L)
As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3
when the power supply is 5.0V and AREF is externally connected to VCC.
The lower limit is:
The upper limit is:
1024 ⋅ 1.5V ⋅ 0,95 ⁄ 5V = 291 = 0x123
1024 ⋅ 1.5V ⋅ 1.05 ⁄ 5V = 323 = 0x143
The recommended values from Table 105 are used unless other values are given in the
algorithm in Table 106. Only the DAC and Port Pin values of the Scan-chain are shown.
The column “Actions” describes what JTAG instruction to be used before filling the
Boundary-scan Register with the succeeding columns. The verification should be done
on the data scanned out when scanning in the data on the same row in the table.
Table 106. Algorithm for Using the ADC(1)
Ste
p
Actions
ADCEN
DAC
PA3. PA3.
MUXEN HOLD PRECH Data Control
PA3.
Pull-
up_
Enable
1
SAMPLE_PRELOAD
1
0x200 0x08
1
1
0
0
0
2
EXTEST
1
0x200 0x08
0
1
0
0
0
3
1
0x200 0x08
1
1
0
0
0
4
1
0x123 0x08
1
1
0
0
0
5
1
0x123 0x08
1
0
0
0
0
6
Verify the COMP bit scanned out to be 0
1
0x200 0x08
1
1
0
0
0
7
1
0x200 0x08
0
1
0
0
0
8
1
0x200 0x08
1
1
0
0
0
9
1
0x143 0x08
1
1
0
0
0
10
1
0x143 0x08
1
0
0
0
0
11 Verify the COMP bit scanned out to be 1
1
0x200 0x08
1
1
0
0
0
Note:
1. Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock frequency. As the algorithm keeps
HOLD high for five steps, the TCK clock frequency has to be at least five times the number of scan bits divided by the maxi-
mum hold time, thold,max.
2490G–AVR–03/04
269
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