• TMS, ADC5 – Port F, Bit 5
ADC5, Analog to Digital Converter, Channel 5.
TMS, JTAG Test mode Select: This pin is used for navigating through the TAP-controller
state machine. When the JTAG interface is enabled, this pin can not be used as an I/O
pin.
• TCK, ADC4 – Port F, Bit 4
ADC4, Analog to Digital Converter, Channel 4.
TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG inter-
face is enabled, this pin can not be used as an I/O pin.
• ADC3 - ADC0 – Port F, Bit 3..0
Analog to Digital Converter, Channel 3..0.
Table 43. Overriding Signals for Alternate Functions in PF7..PF4
Signal
Name PF7/ADC7/TDI
PF6/ADC6/TDO PF5/ADC5/TMS
PUOE JTAGEN
JTAGEN
JTAGEN
PUOV 1
0
1
DDOE JTAGEN
JTAGEN
JTAGEN
DDOV 0
SHIFT_IR +
0
SHIFT_DR
PVOE 0
JTAGEN
0
PVOV 0
TDO
0
DIEOE JTAGEN
JTAGEN
JTAGEN
DIEOV 0
0
0
DI
–
–
–
AIO
TDI/ADC7 INPUT ADC6 INPUT
TMS/ADC5
INPUT
PF4/ADC4/TCK
JTAGEN
1
JTAGEN
0
0
0
JTAGEN
0
–
TCKADC4 INPUT
82 ATmega64(L)
2490G–AVR–03/04