ATXMEGA32D4-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATXMEGA32D4-CU Datasheet PDF : 136 Pages
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XMEGA D4
7.5 Data Memory
The data memory contains the I/O memory, internal SRAM, optionally memory mapped
EEPROM, and external memory if available. The data memory is organized as one continuous
memory section, see Figure 7-2. To simplify development, I/O Memory, EEPROM and SRAM
will always have the same start addresses for all Atmel AVR XMEGA devices.
Figure 7-2. Data memory map (Hexadecimal address).
Byte address
ATxmega64D4
Byte address
ATxmega32D4
Byte address
ATxmega16D4
0
I/O Registers
FFF
(4K)
0
I/O Registers
FFF
(4K)
0
I/O Registers
FFF
(4K)
1000
17FF
EEPROM
(2K)
1000
13FF
EEPROM
(1K)
1000
13FF
EEPROM
(1K)
RESERVED
RESERVED
RESERVED
2000
2FFF
Internal SRAM
(4K)
2000
2FFF
Internal SRAM
(4K)
2000
27FF
Internal SRAM
(2K)
Byte address
0
FFF
1000
17FF
2000
3FFF
ATxmega128D4
I/O Registers
(4K)
EEPROM
(2K)
RESERVED
Internal SRAM
(8K)
7.6 EEPROM
All devices have EEPROM for nonvolatile data storage. It is either addressable in a separate
data space (default) or memory mapped and accessed in normal data space. The EEPROM
supports both byte and page access. Memory mapped EEPROM allows highly efficient
EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is accessible using
load and store instructions. Memory mapped EEPROM will always start at hexadecimal address
0x1000.
7.7 I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are
addressable through I/O memory locations. All I/O locations can be accessed by the load
(LD/LDS/LDD) and store (ST/STS/STD) instructions, which are used to transfer data between
the 32 registers in the register file and the I/O memory. The IN and OUT instructions can
address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 -
0x1F, single-cycle instructions for manipulation and checking of individual bits are available.
15
8135L–AVR–06/12
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