ATXMEGA32D4-CU View Datasheet(PDF) - Atmel Corporation
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ATXMEGA32D4-CU Datasheet PDF : 136 Pages
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XMEGA D4
7.7.1
The I/O memory address for all peripherals and modules in XMEGA D4 is shown in the ”Periph-
eral Module Address Map” on page 56.
General Purpose I/O Registers
The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These reg-
isters can be used for storing global variables and flags, as they are directly bit-accessible using
the SBI, CBI, SBIS, and SBIC instructions.
7.8 Data Memory and Bus Arbitration
Since the data memory is organized as four separate sets of memories, the bus masters (CPU,
etc.) can access different memory sections at the same time.
7.9 Memory Timing
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes
one cycle, and a read from SRAM takes two cycles. EEPROM page load (write) takes one cycle,
and three cycles are required for read. For burst read, new data are available every second
cycle. Refer to the instruction summary for more details on instructions and instruction timing.
7.10
Device ID and Revision
Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the
device and the device type. A separate register contains the revision number of the device.
7.11
I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this,
it is possible to lock the I/O register related to the clock system, the event system, and the
advanced waveform extensions. As long as the lock is enabled, all related I/O registers are
locked and they can not be written from the application software. The lock registers themselves
are protected by the configuration change protection mechanism.
7.12 Flash and EEPROM Page Size
Devices
ATxmega16D4
ATxmega32D4
ATxmega64D4
ATxmega128D4
The flash program memory and EEPROM data memory are organized in pages. The pages are
word accessible for the flash and byte accessible for the EEPROM.
Table 7-2 shows the Flash Program Memory organization and Program Counter (PC) size.
Flash write and erase operations are performed on one page at a time, while reading the Flash
is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The
most significant bits in the address (FPAGE) give the page number and the least significant
address bits (FWORD) give the word in the page.
Table 7-2.
PC size Flash size
[bits]
[bytes]
14
16K + 4K
15
32K + 4K
16
64K + 4K
17
128K + 8K
Number of words and pages in the flash.
Page size FWORD
FPAGE
Application
[words]
Size
No of pages
128
Z[6:0]
Z[13:7]
16K
64
128
Z[6:0]
Z[14:7]
32K
128
128
Z[6:0]
Z[15:7]
64K
256
128
Z[8:0]
Z[16:7]
128K
512
Boot
Size
No of pages
4K
16
4K
16
4K
16
8K
32
16
8135L–AVR–06/12
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