ATXMEGA32D4-CU View Datasheet(PDF) - Atmel Corporation
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Description
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ATXMEGA32D4-CU Datasheet PDF : 136 Pages
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XMEGA D4
32.13.5 Internal Phase Locked Loop (PLL) characteristics
Table 32-23. Internal PLL characteristics.
Symbo
l
Parameter
Condition
Min.
Typ.
Max. Units
fIN
Input frequency
fOUT
Output frequency (1)
Start-up time
Re-lock time
Output frequency must be within fOUT
0.4
VCC= 1.6 - 1.8V
20
VCC= 2.7 - 3.6V
20
64
48
MHz
128
25
µs
25
Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times
the maximum CPU frequency.
32.13.6 External clock characteristics
Figure 32-3. External clock drive waveform.
tCH
tCH
tCR
tCF
VIH1
VIL1
tCL
tCK
Table 32-24. External clock used as system clock without prescaling.
Symbo
l
Parameter
Condition
Min.
Typ.
Max. Units
1/tCK Clock frequency(1)
VCC = 1.6 - 1.8V
0
VCC = 2.7 - 3.6V
0
12
MHz
32
tCK
Clock period
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
83.3
31.5
tCH
Clock high time
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
30.0
12.5
tCL
Clock low time
VCC = 1.6 - 1.8V
30.0
ns
VCC = 2.7 - 3.6V
12.5
VCC = 1.6 - 1.8V
10
tCR
Rise time (for maximum frequency)
VCC = 2.7 - 3.6V
3
VCC = 1.6 - 1.8V
10
tCF
Fall time (for maximum frequency)
VCC = 2.7 - 3.6V
3
ΔtCK Change in period from one clock cycle to the next
10
%
Note: 1. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters
with supply voltage conditions.
76
8135L–AVR–06/12
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