C8051F002 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F002

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

Figure 19.4. TCON: Timer Control Register

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

(bit addressable)

0x88

Bit7:

TF1: Timer 1 Overflow Flag.

Set by hardware when Timer 1 overflows. This flag can be cleared by software but is

automatically cleared when the CPU vectors to the Timer 1 interrupt service routine.

0: No Timer 1 overflow detected.

1: Timer 1 has overflowed.

Bit6:

TR1: Timer 1 Run Control.

0: Timer 1 disabled.

1: Timer 1 enabled.

Bit5:

TF0: Timer 0 Overflow Flag.

Set by hardware when Timer 0 overflows. This flag can be cleared by software but is

automatically cleared when the CPU vectors to the Timer 0 interrupt service routine.

0: No Timer 0 overflow detected.

1: Timer 0 has overflowed.

Bit4:

TR0: Timer 0 Run Control.

0: Timer 0 disabled.

1: Timer 0 enabled.

Bit3:

IE1: External Interrupt 1.

This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can

be cleared by software but is automatically cleared when the CPU vectors to the External

Interrupt 1 service routine if IT1 = 1. This flag is the inverse of the /INT1 input signal’s

logic level when IT1 = 0.

Bit2:

IT1: Interrupt 1 Type Select.

This bit selects whether the configured /INT1 signal will detect falling edge or active-low

level-sensitive interrupts.

0: /INT1 is level triggered.

1: /INT1 is edge triggered.

Bit1:

IE0: External Interrupt 0.

This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can

be cleared by software but is automatically cleared when the CPU vectors to the External

Interrupt 0 service routine if IT0 = 1. This flag is the inverse of the /INT0 input signal’s

logic level when IT0 = 0.

Bit0:

IT0: Interrupt 0 Type Select.

This bit selects whether the configured /INT0 signal will detect falling edge or active-low

level-sensitive interrupts.

0: /INT0 is level triggered.

1: /INT0 is edge triggered.

Rev. 1.7

142

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