C8051F002 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F002

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

Figure 19.6. CKCON: Clock Control Register

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

-

-

T2M

T1M

T0M

Reserved Reserved Reserved 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0x8E

Bits7-6: UNUSED. Read = 00b, Write = don’t care.

Bit5:

T2M: Timer 2 Clock Select.

This bit controls the division of the system clock supplied to Timer 2. This bit is ignored

when the timer is in baud rate generator mode or counter mode (i.e. C/T2 = 1).

0: Timer 2 uses the system clock divided by 12.

1: Timer 2 uses the system clock.

Bit4:

T1M: Timer 1 Clock Select.

This bit controls the division of the system clock supplied to Timer 1.

0: Timer 1 uses the system clock divided by 12.

1: Timer 1 uses the system clock.

Bit3:

T0M: Timer 0 Clock Select.

This bit controls the division of the system clock supplied to Counter/Timer 0.

0: Counter/Timer uses the system clock divided by 12.

1: Counter/Timer uses the system clock.

Bits2-0: Reserved. Read = 000b, Must Write = 000.

Rev. 1.7

144

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