C8051F045 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

11. Comparators

C8051F04x family of devices include three on-chip programmable voltage comparators, shown in

Figure 11.1. Each comparator offers programmable response time and hysteresis. When assigned to a

Port pin, the Comparator output may be configured as open drain or push-pull, and Comparator inputs

should be configured as analog inputs (see Section “17.1.5. Configuring Port 1, 2, and 3 Pins as Ana-

log Inputs” on page 207). The Comparator may also be used as a reset source (see Section

“13.5. Comparator0 Reset” on page 167).

The output of a Comparator can be polled by software, used as an interrupt source, used as a reset

source, and/or routed to a Port pin. Each comparator can be individually enabled and disabled (shutdown).

When disabled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic

low state, and its supply current falls to less than 1 µA. See Section “17.1.1. Crossbar Pin Assignment

and Allocation” on page 205 for details on configuring the Comparator output via the digital Crossbar.

The Comparator inputs can be externally driven from -0.25 V to (VDD) + 0.25 V without damage or upset.

The complete electrical specifications for the Comparator are given in Table 11.1.

The Comparator response time may be configured in software using the CPnMD1-0 bits in register CPT-

nMD (see SFR Definition 11.2). Selecting a longer response time reduces the amount of power consumed

by the comparator. See Table 11.1 for complete timing and current consumption specifications.

CPnEN

CPnOUT

CPnRIF

CPnFIF

CPnHYP1

CPnHYP0

CPnHYN1

CPnHYN0

Comparator Pin Assignments

CP0 +

CP0 -

P2.6

P2.7

CP1 +

CP1 -

P2.2

P2.3

CP2 +

CP2 -

P2.4

P2.5

CPn +

CPn -

VDD

CPn

Interrupt

CPn

Rising-edge

Interrupt Flag

CPn

Falling-edge

Interrupt Flag

+

SET

DQ

SET

DQ

-

Q

CLR

Q

CLR

(SYNCHRONIZER)

GND

Reset

Decision

Tree

Interrupt

Logic

CPn

Crossbar

CPnRIEN

CPnFIEN

CPnMD1

CPnMD0

Figure 11.1. Comparator Functional Block Diagram

Rev. 1.5

121

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