C8051F045 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

13.7.1. Enable/Reset WDT

The watchdog timer is both enabled and reset by writing 0xA5 to the WDTCN register. The user's applica-

tion software should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog timer

overflow. The WDT is enabled and reset as a result of any system reset.

13.7.2. Disable WDT

Writing 0xDE followed by 0xAD to the WDTCN register disables the WDT. The following code segment

illustrates disabling the WDT:

CLR

MOV

MOV

SETB

EA

WDTCN,#0DEh

WDTCN,#0ADh

EA

; disable all interrupts

; disable software watchdog timer

; re-enable interrupts

The writes of 0xDE and 0xAD must occur within 4 clock cycles of each other, or the disable operation is

ignored. Interrupts should be disabled during this procedure to avoid delay between the two writes.

13.7.3. Disable WDT Lockout

Writing 0xFF to WDTCN locks out the disable feature. Once locked out, the disable operation is ignored

until the next system reset. Writing 0xFF does not enable or reset the watchdog timer. Applications always

intending to use the watchdog should write 0xFF to WDTCN in the initialization code.

13.7.4. Setting WDT Interval

WDTCN.[2:0] control the watchdog timeout interval. The interval is given by the following equation:

43 + WDTCN2 – 0  Tsysclk ; where Tsysclk is the system clock period.

For a 3 MHz system clock, this provides an interval range of 0.021 ms to 349.5 ms. WDTCN.7 must be

logic 0 when setting this interval. Reading WDTCN returns the programmed interval. WDTCN.[2:0] reads

111b after a system reset.

168

Rev. 1.5

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