C8051F045 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

SFR Definition 13.2. RSTSRC: Reset Source

R

-

Bit7

Bit7:

Bit6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

R/W

R/W

R/W

R

R/W

CNVRSEF C0RSEF SWRSEF WDTRSF MCDRSF

Bit6

Bit5

Bit4

Bit3

Bit2

R

PORSF

Bit1

R/W

Reset Value

PINRSF 00000000

Bit0

SFR Address: 0xEF

SFR Page: 0

Reserved.

CNVRSEF: Convert Start Reset Source Enable and Flag

Write: 0: CNVSTR0 is not a reset source.

1: CNVSTR0 is a reset source (active low).

Read: 0: Source of prior reset was not CNVSTR0.

1: Source of prior reset was CNVSTR0.

C0RSEF: Comparator0 Reset Enable and Flag.

Write: 0: Comparator0 is not a reset source.

1: Comparator0 is a reset source (active low).

Read: 0: Source of last reset was not Comparator0.

1: Source of last reset was Comparator0.

SWRSF: Software Reset Force and Flag.

Write: 0: No effect.

1: Forces an internal reset. /RST pin is not effected.

Read: 0: Source of last reset was not a write to the SWRSF bit.

1: Source of last reset was a write to the SWRSF bit.

WDTRSF: Watchdog Timer Reset Flag.

0: Source of last reset was not WDT timeout.

1: Source of last reset was WDT timeout.

MCDRSF: Missing Clock Detector Flag.

Write: 0: Missing Clock Detector disabled.

1: Missing Clock Detector enabled; triggers a reset if a missing clock condition is

detected.

Read: 0: Source of last reset was not a Missing Clock Detector timeout.

1: Source of last reset was a Missing Clock Detector timeout.

PORSF: Power-On Reset Flag.

Write: If the VDD monitor circuitry is enabled (by tying the MONEN pin to a logic high state), this

bit can be written to select or de-select the VDD monitor as a reset source.

0: De-select the VDD monitor as a reset source.

1: Select the VDD monitor as a reset source.

Important: At power-on, the VDD monitor is enabled/disabled using the external VDD moni-

tor enable pin (MONEN). The PORSF bit does not disable or enable the VDD monitor cir-

cuit. It simply selects the VDD monitor as a reset source.

Read: This bit is set whenever a power-on reset occurs. This may be due to a true power-on

reset or a VDD monitor reset. In either case, data memory should be considered indeterminate

following the reset.

0: Source of last reset was not a power-on or VDD monitor reset.

1: Source of last reset was a power-on or VDD monitor reset.

Note: When this flag is read as '1', all other reset flags are indeterminate.

PINRSF: HW Pin Reset Flag.

Write: 0: No effect.

1: Forces a Power-On Reset. /RST is driven low.

Read: 0: Source of prior reset was not /RST pin.

1: Source of prior reset was /RST pin.

170

Rev. 1.5

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