C8051F045 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
Manufacturer
C8051F045 Datasheet PDF : 328 Pages
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C8051F040/1/2/3/4/5/6/7
P0
P1
P2
P3
PIN I/O 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
TX0
z
RX0
z
SCK
zz
MISO
zz
MOSI
zz
NSS
z z NSS is not assigned to a port pin when the SPI is placed in 3-wire mode
SDA
z zzzzz
SCL
z zzzzz
TX1
z zzzzzzz
RX1
z zzzzzzz
CEX0
z
zzzzzzzzz
CEX1
z zzzzzzzzz
CEX2
z zzzzzzzzz
CEX3
z zzzzzzzzz
CEX4
z zzzzzzzzz
CEX5
z
zzzzzzzzz
ECI
zzzzzzzzzzzzzzzzz
CP0
zzzzzzzzzzzzzzzzzz
CP1
zzzzzzzzzzzzzzzzzzz
CP2
zzzzzzzzzzzzzzzzzzzz
T0
zzzzzzzzzzzzzzzzzzzzz
/INT0
zzzzzzzzzzzzzzzzzzzzzz
T1
zzzzzzzzzzzzzzzzzzzzzzz
/INT1 z z z z z z z z z z z z z z z z z z z z z z z z
T2
zzzzzzzzzzzzzzzzzzzzzzzzz
T2EX z z z z z z z z z z z z z z z z z z z z z z z z z z
T3
zzzzzzzzzzzzzzzzzzzzzzzzzzz
T3EX z z z z z z z z z z z z z z z z z z z z z z z z z z z z
T4
zzzzzzzzzzzzzzzzzzzzzzzzzzzzz
T4EX z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z
/SYSCLK z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z
CNVSTR0 z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z
CNVSTR2 z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z
Crossbar Register Bits
UART0EN: XBR0.2
SPI0EN: XBR0.1
SMB0EN: XBR0.0
UART1EN: XBR2.2
PCA0ME: XBR0.[5:3]
ECI0E: XBR0.6
CP0E: XBR0.7
CP1E: XBR1.0
CP2E: XBR3.3
T0E: XBR1.1
INT0E: XBR1.2
T1E: XBR1.3
INT1E: XBR1.4
T2E: XBR1.5
T2EXE: XBR1.6
T3E: XBR3.0
T3EXE: XBR3.1
T4E: XBR2.3
T4EXE: XBR2.4
SYSCKE: XBR1.7
CNVSTE0: XBR2.0
CNVSTE2: XBR3.2
AIN1 Inputs/Non-muxed Addr H Muxed Addr H/Non-muxed Addr L Muxed Data/Non-muxed Data
Figure 17.3. Priority Crossbar Decode Table
(EMIFLE = 0; P1MDIN = 0xFF)
17.1.1. Crossbar Pin Assignment and Allocation
The Crossbar assigns Port pins to a peripheral if the corresponding enable bits of the peripheral are set to
a logic 1 in the Crossbar configuration registers XBR0, XBR1, XBR2, and XBR3, shown in SFR Definition
17.1, SFR Definition 17.2, SFR Definition 17.3, and SFR Definition 17.4. For example, if the UART0EN bit
(XBR0.2) is set to a logic 1, the TX0 and RX0 pins will be mapped to P0.0 and P0.1 respectively. Because
UART0 has the highest priority, its pins will always be mapped to P0.0 and P0.1 when UART0EN is set to
a logic 1. If a digital peripheral’s enable bits are not set to a logic 1, then its ports are not accessible at the
Port pins of the device. Also note that the Crossbar assigns pins to all associated functions when a serial
communication peripheral is selected (i.e. SMBus, SPI, UART). It would be impossible, for example, to
assign TX0 to a Port pin without assigning RX0 as well. Each combination of enabled peripherals results in
a unique device pinout.
All Port pins on Ports 0 through 3 that are not allocated by the Crossbar can be accessed as General-Pur-
pose I/O (GPIO) pins by reading and writing the associated Port Data registers (See SFR Definition 17.5,
Rev. 1.5
205
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